Analysis of worst-case delay bounds for on-chip packet-switching networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 5, 2010, Pages 802-815

  Qian, Yue ^a   Lu, Zhonghai ^b   Dou, Wenhua ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Delay bound; Network calculus; Network on chip; Performance analysis; Quality of service

Indexed keywords

ANALYSIS TECHNIQUES; CLOSED-FORM FORMULAE; COMMUNICATION DELAYS; DELAY BOUND; IN-NETWORK; NETWORK CALCULUS; NETWORK CONTENTION; NETWORK ON CHIP; ON CHIPS; PACKET DELAY; PACKET DELIVERY; THEORETICAL BOUNDS; TOPOLOGY-INDEPENDENT;

CALCULATIONS; SWITCHING NETWORKS; VLSI CIRCUITS;

QUALITY CONTROL;

EID: 77951675199     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2043572     Document Type: Article

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