LOFT: A high performance network-on-chip providing quality-of-service support

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 409-420

  Ouyang, Jin ^a   Xie, Yuan ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT TASKS; CONTROL MECHANISM; DISTRIBUTED-FRAME; HIGH PERFORMANCE NETWORKS; IN-CHIP; MANY-CORE ARCHITECTURE; MEMORY CONTROLLER; NET WORK UTILIZATION; NETWORK CAPACITY; NETWORK ON CHIP; NOC ARCHITECTURES; ON CHIPS; QOS GUARANTEE; QOS SUPPORT; REAL-TIME APPLICATION; SCALABLE PERFORMANCE; SHARED CACHE; SHARED RESOURCES;

BUILDINGS; NETWORK ARCHITECTURE; ROUTERS; SERVERS; VLSI CIRCUITS;

QUALITY OF SERVICE;

EID: 79951703135     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.21     Document Type: Conference Paper

References (25)

1. Intel CoreTM i7 Processor Families. Intel Corporation. [Online]. Available: http://www.intel.com/design/corei7/
2. L. Seiler, D. Carmean, E. Sprangle et al., "Larrabee: a many-core x86 architecture for visual computing," ACM Trans. Graphics, vol. 27, no. 3, pp. 1-15, 2008.
3. Tilera Processor Families. Tilera Corporation. [Online]. Available: http://www.tilera.com/products/processors.php
4. T. G. Mattson, R. Van der Wijngaart, and M. Frumkin, "Programming the Intel 80-core network-on-a-chip terascale processor," in Proc. of Conference on Supercomputing, 2008, pp. 1-11.
5. J. Howard, S. Dighe, Y. Hoskote et al., "A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS," in Digest of Technical Papers in Solid-State Circuits Conference, 7-11 2010, pp. 108-109.
6. R. Iyer, "CQoS: a framework for enabling QoS in shared caches of CMP platforms," in Proc. of International Conference on Supercomputing, 2004, pp. 257-266.
7. K. J. Nesbit, J. Laudon, and J. E. Smith, "Virtual private caches," in Proc. of International Symposium on Computer architecture, 2007, pp. 57-68. (Pubitemid 47582091)
8. S. Srikantaiah, R. Das, A. K. Mishra et al., "A case for integrated processor-cache partitioning in chip multiprocessors," in Proc. of the Conference on High Performance Computing Networking, Storage and Analysis, 2009, pp. 1-12.
9. K. J. Nesbit, N. Aggarwal, J. Laudon et al., "Fair queuing memory systems," in Proc. of International Symposium on Microarchitecture, 2006, pp. 208-222.
10. O. Mutlu and T. Moscibroda, "Stall-time fair memory access scheduling for chip-multiprocessors," in Proc. of International Symposium on Microarchitecture, 2007, pp. 146-160.
11. E. Ebrahimi, C. J. Lee, O. Mutlu et al., "Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems," in Proc. of Architectural Support for Programming Languages and Operating Systems, 2010, pp. 335-346.
12. J. W. Lee, M. C. Ng, and K. Asanovic, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in Proc. of International Symposium on Computer Architecture, 2008, pp. 89-100.
13. B. Grot, S. W. Keckler, and O. Mutlu, "Preemptive virtual clock: a flexible, efficient, and cost-effective QoS scheme for networks-on-chip," in Proc. of International Symposium on Microarchitecture, 2009, pp. 268-279.
14. K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal network on chip: concepts, architectures, and implementations," IEEE Trans. esign and Test, vol. 22, no. 5, pp. 414-421, 2005. (Pubitemid 41522729)
15. M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip," in Proc. of Conference on Design, Automation and Test in Europe, 2004, pp. 890-895.
16. T. Bjerregaard and J. Sparso, "A router architecture for connectionoriented service guarantees in the MANGO clockless network-on-chip," in Proc. of Conference on Design, Automation and Test in Europe, 2005, pp. 1226-1231. (Pubitemid 44172177)
17. W.-D. Weber, J. Chou, I. Swarbrick, and D. Wingard, "A quality-ofservice mechanism for interconnection networks in system-on-chips, " in Proc. of Conference on Design, Automation and Test in Europe, 2005, pp. 1232-1237. (Pubitemid 44172178)
18. J. H. Kim and A. A. Chien, "Rotating combined queueing (RCQ): bandwidth and latency guarantees in low-cost, high-performance networks," in Proc. International Symposium on Computer architecture, 1996, pp. 226-236.
19. R. Das, O. Mutlu, T. Moscibroda, and C. R. Das, "Application-aware prioritization mechanisms for on-chip networks," in Proc. of International Symposium on Microarchitecture, 2009, pp. 280-291.
20. L.-S. Peh and W. J. Dally, "Flit-reservation flow control," IEEE Trans. on Parallel and Distributed Systems, vol. 3, no. 3, pp. 194-205, 2000.
21. H. Zhang and S. Keshav, "Comparison of rate-based service disciplines," in Proc. of Conference on Communications architecture & protocols, 1991, pp. 113-121.
22. J. Kim, D. Park, C. Nicopoulos, N. Vijaykrishnan, and C. R. Das, "Design and analysis of an NoC architecture from performance, reliability and energy perspective," in Proc. of ACM symposium on Architecture for Networking and Communications Systems, 2005, pp. 173-182.
23. L.-S. Peh and W. J. Dally, "A delay model and speculative architecture for pipelined routers," in Proc. of International Symposium on High-Performance Computer Architecture, 2001, p. 255.
24. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," in Proc. of International Symposium on Microarchitecture, 2009, pp. 469-480.
25. D. Vantrease, N. Binkert, R. Schreiber, and M. H. Lipasti, "Light speed arbitration and flow control for nanophotonic interconnects," in Proc. of International Symposium on Microarchitecture, 2009, pp. 304-315.