Spintronics for low-power computing

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Zhang, Yue ^a   Zhao, Weisheng ^a,b   Klein, Jacques Olivier ^a,b   Kang, Wang ^a,c   Querlioz, Damien ^a,b   Zhang, Youguang ^c   Ravelosona, Dafiné ^a,b   Chappert, Claude ^a,b  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b CNRS   (France)

^c BEIHANG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER AIDED DESIGN; MAGNETIC DEVICES; MAGNETIC STORAGE; MAGNETOELECTRONICS; MICROELECTRONICS; NANOSTRUCTURED MATERIALS;

CONTINUOUS IMPROVEMENTS; EMERGING RESEARCH DEVICES; FUTURE CHALLENGES; LOW-POWER COMPUTING; LOW-POWER OPERATION; MAGNETIC TUNNEL JUNCTION; MULTI DISCIPLINES; OPERATING FREQUENCY;

NANOTECHNOLOGY;

EID: 84903850443     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.316     Document Type: Conference Paper

References (51)

1. International Roadmap for semiconductor (ITRS), 2011 ERD Update.
2. N.S. Kim et al., "Leakage current: Moore's law meets the static power", Computer, vol. 36, pp. 68-75, 2003.
3. M. Duranton, "New computing architectures for Green ICT", Chist-era Conference, 2011.
4. C. Chappert, A. Fert and F. Nguyen Van Dau, "The emergence of spin electronics in data storage", Nat. Mater., vol. 6, pp. 813-823, 2007.
5. C.J. Lin et al., "45nm Low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell", Procs. of IEDM, pp. 279-282, 2009.
6. K. Tsuchida et al., "A 64Mb MRAM with clamped-reference and adequate-reference schemes", Procs. of ISSCC, pp. 258-259, 2010.
7. Everspin Corporation, www.everspin.com
8. Y. Zhang et al., "Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions", IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 819-826, 2012.
9. W.S. Zhao et al., "New non-volatile logic based on spin-MTJ", Physica Status Solidi a, vol. 6, pp. 1373-1377, 2008.
10. W.S. Zhao, E. Belhaire, C. Chappert, "Spin-MTJ based Non-Volatile Flip-Flop",Procs. of IEEE-NANO, pp.399-402, 2007.
11. K. Ryu et al., "A magnetic tunnel junction based zero standby leakage current retention Flip-Flop", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 20, pp. 2044 2053, 2012.
12. W.S. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer, "Spin transfer torque (STT)-MRAM based run time reconfiguration FPGA circuit", ACM Trans. Embedded Computing Systems, vol. 9, art. 14, 2009.
13. N. Sakimura, T. Sugibayashi, R. Nebashi, et N. Kasai, "Nonvolatile magnetic Flip-Flop for standby-power-free SoCs", IEEE Journal of Solid-State Circuits, vol. 44, no 8, pp. 2244-2250, 2009.
14. S. Matsunaga et al.,"Fabrication of a nonvolatile full adder based on Logic-in-Memory architecture using magnetic tunnel junctions", Appl. Phys. Express (APEX), vol. 1, 091301, 2008.
15. H. Meng, J. Wang, J. P. Wang, "A Spintronics full adder for magnetic CPU", IEEE Electron Device Lett., vol.26, pp.360-362, 2005.
16. S. Ikeda et al, "A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction", Nat Mater, vol. 9, pp. 721-724, 2010.
17. D. C. Worledge et al., "Spin torque switching of perpendicular Ta|CoFeB|MgO-based magnetic tunnel junctions", Appl. Phys. Lett., vol. 98, p. 022501, 2011.
18. D. A. Allwood et al., "Magnetic domain-wall logic" Science, vol. 309, pp.1688-1692, 2005.
19. S. S. P. Parkin, M. Hayashi, and L. Thomas, "Magnetic domain-wall racetrack memory" Science, vol. 320, no. 5873, pp. 190-4, 2008.
20. Y. Zhang, W.S. Zhao, D. Ravelosona, J-O. Klein, J.V. Kim and C. Chappert, "Perpendicular-magnetic-anisotropy CoFeB racetrack memory", Journal of Applied Physics, vol.111, pp. 093925, 2012.
21. H-P Trinh et al., "Magnetic adder based on racetrack memory", IEEE Transactions on Circuits and Systems I, vol.60, pp.1469-1477, 2013.
22. Y. Zhang et al., "Ultra-High Density Content Addressable Memory based on Current Induced Domain Wall Motion in Magnetic Track" IEEE Transaction on Magnetics, vol.48, pp.3219-3222, 2012.
23. A.J. Annunziata et al., "Racetrack memory cell array with integrated magnetic tunnel junction readout", Procs. of IEDM, pp.24.2.1, 2011.
24. S. Datta and B. Das, "Electronic analog of the electrooptic modulator". Applied Physics Letters, vol. 56, pp. 665-667, 1990.
25. B. Dlubak et al., "Highly efficient spin transport in epitaxial graphene on SiC", Nature Physics, vol.8, pp.557-561, 2012.
26. L. A. Ponomarenko, et al., "Chaotic dirac billiard in graphene quantum dots", Science, vol. 320, pp. 356-358, 2008.
27. H. Dery, et al.,"Nanospintronics Based on Magnetologic Gates" IEEE Trans. on Electron Devices, vol. 59, pp. 259, 2012.
28. R.P. Cowburn and M.E. Welland, "Room temperature magnetic quantum cellular automata", Science, vol. 287, pp.1466-1468, 2000.
29. A. Imre, G. Csaba, L. Ji, A. Orlov, G.H. Bernstein, W. Porod, "Majority Logic Gate for Magnetic Quantum-Dot Cellular Automata," Science, vol. 311, pp. 205-208, 2006.
30. S. Breitkreutz, et al., "Experimental demonstration of a 1-bit full adder in perpendicular nanomagnetic logic", IEEE Trans. on Magnetics, vol.49, pp.4464-4467, 2013.
31. R. Lavrijsen, et al., "Magnetic ratchet for three-dimensional spintronic memory and logic", Nature, vol.493, pp. 647-650, 2013.
32. T. Schneider et al., "Realization of spin-wave logic gates", Appl. Phys. Letters, vol.92, pp. 022505, 2008.
33. A. Khitun, M. Bao, K.L. Wang, "Spin wave magnetic nanofabric: anew approach to spin-based logic circuitry", IEEE Trans. on Magnetics, vol.44, pp.2141-2152, 2008.
34. A. Khitun and K.L. Wang, "Nano scale computional architecturs with spin wave bus", Superlattices and Microstructures, vol. 38, pp. 184-200, 2005.
35. D.B. Strukov, G.S. Snider, D.R. Stewart and R.S. Williams, "The missing memristor found", Nature, vol.453, pp. 80-83, 2008.
36. A. Chanthbouala, et al, "A ferroelectric memristor," Nature Materials, vol. 11, pp. 860-864, 2012.
37. X. Wang, et al., "Spintronic memristor through spin-torque-induced magnetization motion", IEEE Trans. on Electron Device, vol.30, pp. 294-297, 2009.
38. K.H. Kim, et al., "A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications", Nano Letter, vol. 12, pp. 389-395, 2012.
39. S.H. Kang, "Embedded STT-MRAM for mobile applications: enabling advanced chip architectures", Non-volatile Memories Workshop, 2010.
40. H. Yoda, et al., "Progress of STT-MRAM technology and the effect on normally-off computing systems", Procs. of IEDM, pp.11.3.1, 2012.
41. W.S Zhao et al., "High Performance SoC Design Using Magnetic Logic and Memory", Procs. of VLSI-SoC, vol. 379, pp. 10-33, 2012.
42. Y. Zhang et al., "Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications ", IEEE Trans. on Magnetics, vol.49, pp.4375-4378, 2013.
43. W. Kang, et al, "A low-cost built-in error correction circuit design for STT-MRAM reliability improvement," Microelectron. Reliab, vol. 53, pp. 1224-1229, 2013.
44. W.S. Zhao, D. Ravelosona, J-O Klein and C. Chappert, "Domain Wall Shift Register based reconfigurable logic", IEEE Trans. on Magnetics, vol.47, pp.2966-2969, 2011.
45. G. Prenat et al., "CMOS/Magnetic Hybrid Architectures", Procs. of IEEE-ICECS, Morocco, pp.190-193, 2007.
46. W.S. Zhao, E. Belhaire, C. Chappert, G. Prenat, B. Dieny, "TASMRAM based low power, high speed Run-Time Reconfiguration (RTR) FPGA", ACM Trans. on Reconfigurable Technology and Systems, vol.2, article.8, 2009.
47. B. Behin-Aein et al., "Proposal for an all-spin logic device with built-in memory", Nature Nanotechnology, vol.5, pp.266-270, 2010.
48. C. Mead, "Neuromorphic electronic systems," Proc. IEEE, vol. 78, pp. 1629-1636, 2010.
49. X. Wang and Y. Chen., "Spintronic memristor devices and application," Procs. of DATE 2010, pp.667-672, 2010.
50. M. Sharad et al., "Spin-Based Neuron Model With Domain-Wall Magnets as Synapse," IEEE Trans. Nano., Vol. 11, pp. 843-853, 2012.
51. K. Roy et al., "Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices", IEEE ISLPED, pp.139-142, 2013.