Domain wall shift register-based reconfigurable logic

IEEE Transactions on Magnetics

Volumn 47, Issue 10, 2011, Pages 2966-2969

  Zhao, Weisheng ^a,b   Ravelosona, Dafine ^a,b   Klein, Jacques Olivier ^a,b   Chappert, Claude ^a,b  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b CNRS   (France)

Author keywords

Domain wall (DW); high density and hybrid DW CMOS logic; high speed; low power; magnetic tunnel junction (MTJ); nonvolatile

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; DOMAIN WALLS; LOGIC CIRCUITS; LOW POWER ELECTRONICS; MAGNETIC DEVICES; MAGNETIC HEADS; MAGNETISM; SHIFT REGISTERS; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP; TUNNEL JUNCTIONS;

HIGH DENSITY AND HYBRID DW/CMOS LOGIC; HIGH SPEED; LOW POWER; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE;

RECONFIGURABLE HARDWARE;

EID: 80053482045     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2011.2158294     Document Type: Article

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