TAS-MRAM-based low-power high-speed runtime reconfiguration (RTR) FPGA

ACM Transactions on Reconfigurable Technology and Systems

Volumn 2, Issue 2, 2009, Pages

  Zhao, Weisheng ^a   Belhaire, Eric ^a   Chappert, Claude ^b   Dieny, Bernard ^c   Prenat, Guillaume ^c  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b CNRS   (France)

^c CEA GRENOBLE   (France)

Author keywords

Design; Experimentation

Indexed keywords

COMPUTING ARCHITECTURE; DESIGN TECHNIQUE; EXPERIMENTATION; FIELD INDUCED; HIGH-POWER; HIGH-SPEED; LARGE CIRCUITS; LOGIC COMPONENTS; LOGIC FUNCTIONS; LOW POWER; MAGNETIC SWITCHING; MEMORY CELL; MRAM TECHNOLOGY; NONVOLATILITY; READING SPEED; RUN-TIME RECONFIGURATION; SPICE MODEL; SPINTRONICS APPLICATION; STMICROELECTRONICS;

COMPUTER SIMULATION; DESIGN; LOGIC DESIGN; MAGNETIC DEVICES; MRAM DEVICES; NANOTECHNOLOGY; SPICE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70449353237     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1534916.1534918     Document Type: Article

References (18)

1. BROWN, S., FRANCIS, R., ROSE, J., AND VRANESIC, Z. 1992. Field-Programmable Gate Arrays. Kluwer Academic.
2. INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS (ITRS). 2007. Process integration, devices and structures. 24-25.
3. GALLAGHER, W. J. AND PARKIN, S. S. P. 2006. Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip. IBM J. Res. Develop. 5-23. (Pubitemid 43257586)
4. MORRIS, K. 2005. Flash news flash. FPGA Program. Logic J. 1-4.
5. KIM, N. S. 2003. Leakage current: Moore's law meets the static power. IEEE Comput. Soc. 68-74.
6. PREJBEANU, I. L., KULA, W., OUNADJELA, K., SOUSA, R. C., REDON, O., DIENY, D., AND NOZIERES, J. P. 2004. Thermally assisted switching in exchange-biased storage layer magnetic tunnel junctions. IEEE Trans. Magnetics, 2625-2627.
7. PREJBEANU, I. L., KEREKES, M., SOUSA, R. C., SIBUET, H., REDON, O., DIENY, D. AND NOZIERES, J. P. 2007. Thermally assisted MRAM. J. Phys. Condensed Matter 19, 165-218.
8. RAPPITSCH, G. 2003. Statistical SPICE modeling for analog circuit design. In Proceedings of the IEEE ESSCIRC.
9. REDON, O., KEREKES, M., SOUSA, R., PREJBEANU, L., SIBUET, H., PONTHENNIER, F., PERSICO, A., AND NOZIÈRES, J. P. 2005. Thermo assistedMRAM for low power applications. In Proceedings of the 1st International Conference on Memory Technology and Design (ICMTD'05). 113-114.
10. STMICROELECTRONICS. 2007. Manuel of design kit for CMOS 90nm.
11. STOJANOVIC, V. AND OKLOBDZIJA, V. G. 1999. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Solid-State Circ. 536-548.
12. SUN, J. Z. 2006. Spin angular momentum transfer in current-perpendicular nanomagnetic junctions. IBM J. Res. Develop. 81-100. (Pubitemid 43257590)
13. WOLF, S., AWSCHALOM, D., BUHRMAN, R., DAUGHTON, J., VON MOULNAR, S., ROUKES, M., CHTCHELKANOVA, A., AND TREGER, M. 2001. Spintronics: A spin-based electronics vision for the future: Magnetism and materials. Science, 1488-1495. (Pubitemid 33063913)
14. XILINX CORP. Virtex-4 configuration guide. http://www.xilinx.com/support/ documentation/user guides/ug071.pdf.
15. YUASA, S., NAGAHAMA, T., FUKUSHIMA, A., SUZUKI, Y., AND ANDO, K. 2004. Giant roomtemperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions. Nat. Mater. 868-871.
16. ZHAO, W., BELHAIRE, E., JAVERLIAC, J., CHAPPERT, C., AND DIENY, B. 2006a. Evaluation of a nonvolatile FPGA based on MRAM technology. In Proceedings of the IEEE International Confer- ence on Integrated Circuit Design and Technology. 17-21.
17. ZHAO, W., BELHAIRE, E., JAVERLIAC, J., CHAPPERT, C., AND DIENY, B. 2006b. A nonvolatile flip-flop in magnetic FPGA chip. In Proceedings of the IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology. 323-326.
18. ZHAO, W., BELHAIRE, E., CHAPPERT, C., JACQUET, F., AND MAZOYER, P. 2008. New nonvolatile logic based on Spin-MTJ. Phys. Status Solidi-a: Appl. Mater. Sci. 205, 6, 1373-1377.