A low-power Low-VDD nonvolatile latch using spin transfer torque MRAM

IEEE Transactions on Nanotechnology

Volumn 12, Issue 6, 2013, Pages 1094-1103

  Huang, Kejie ^a,b   Lian, Yong ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b DATA STORAGE INSTITUTE   (Singapore)

Author keywords

Low power; Nonvolatile flip flop (nvFF); Nonvolatile latch (nvLatch); Nonvolatile memory (NVM); Spin torque transfer MRAM (STT MRAM); Two phase write approach

Indexed keywords

LOW POWER; NON-VOLATILE; NON-VOLATILE FLIP-FLOPS; NON-VOLATILE MEMORY; STT-MRAM; TWO-PHASE WRITE APPROACH;

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; SLEEP RESEARCH;

MRAM DEVICES;

EID: 84888182558     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2013.2280338     Document Type: Article

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