Negative-resistance read and write schemes for STT-MRAM in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 256-257

  Halupka, David ^a   Huda, Safeen ^a   Song, William ^a   Sheikholeslami, Ali ^a   Tsunoda, Koji ^b   Yoshida, Chikako ^b   Aoki, Masaki ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS SCHEMES; CMOS COMPATIBLE; DEVICE VARIATIONS; EMERGING NON-VOLATILE MEMORY TECHNOLOGY; HIGH-POWER; HIGH-SPEED ACCESS; MAGNETIC SWITCHING; MAGNETORESISTIVE; NON DESTRUCTIVE; POWER CONSUMPTION; RANDOM ACCESS MEMORIES; SPIN TORQUE; TEST-CHIP;

CMOS INTEGRATED CIRCUITS; MAGNETIC STORAGE;

MRAM DEVICES;

EID: 77952215289     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433943     Document Type: Conference Paper

References (6)

1. T. Kawahara et al., "2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read," ISSCC, pp. 480-481, 2007.
2. M. Hosomi et al., "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM," IEDM, pp. 459-462, 2005.
3. C. Yoshida et al., "A Study of Dielectric Breakdown Mechanism in CoFeB/MgO/CoFeB Magnetic Tunnel Junction," IRPS, pp. 139-142, 2009.
4. J. Nahas et al., "A 180 Kbit Embeddable MRAM Memory Module," JSSC, vol. 43, no. 8, pp. 1826-1834, 2008.
5. R. Nebashi et al., "A 90nm 12ns 32Mb 2T1MTJ MRAM," ISSCC, pp. 462-463, 2009.
6. O.Tyshchenko, A.Sheikholeslami, "Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM)," JSSC, vol. 43, no. 9, pp. 1972-1981, 2008.