Restructuring of memory hierarchy in computing system with spintronics-based technologies

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 89-90

  Endoh, Tetsuo ^a   Ohsawa, Takashi ^a   Koike, Hiroki ^a   Hanyu, Takahiro ^a   Ohno, Hideo ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER MEMORIES; COMPUTING SYSTEM; CORE CIRCUIT; MAGNETIC TUNNEL JUNCTION; MEMORY HIERARCHY; PERFORMANCE GAIN; POWER REDUCTIONS; SENSE AMPLIFIER;

CACHE MEMORY; FLIP FLOP CIRCUITS; STATIC RANDOM ACCESS STORAGE;

MAGNETIC DEVICES;

EID: 84866564548     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242475     Document Type: Conference Paper

References (9)

1. T. Endoh, ITRS Emerging Research Memory Technology Workshop, 2010.
2. T. Endoh, STS in SEMICON Korea (invited), 2010.
3. H. Ohno et al., IEDM, pp. 218-221, 2010.
4. T. Ohsawa et al., SSDM, pp. 959-960, 2011.
5. T. Ohsawa et al., JJAP, 51 (2012) 02BD01.
6. Y. M. Lee et al., Symp. VLSI Tech., pp. 49-50, 2010.
7. C. J. Lin et al., IEDM, pp. 279-282, 2009.
8. H. Koike and T. Endoh, VLSI-TSA, pp. 56-57, 2011.
9. T. Endoh et al., IEDM, pp. 75-78, 2011