Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing

2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

Volumn , Issue , 2013, Pages

  Torres, Lionel ^a   Brum, Raphael Martins ^a   Guillemenet, Yoann ^a   Sassatelli, Gilles ^a   Cargnini, Luis Vitirio ^a  

^a LIRMM   (France)

Author keywords

Hybrid MRAM CMOS cells; Reconfigurable Computing; TAS MRAM

Indexed keywords

ADVANCED TECHNOLOGY; BASIC ELEMENTS; CONFIGURATION MEMORY; MRAM TECHNOLOGY; PROGRAMMABLE LOGIC; RECONFIGURABLE COMPUTING; SPIN TRANSFER TORQUE; TAS MRAM;

CYTOLOGY; DESIGN; MRAM DEVICES; RECONFIGURABLE ARCHITECTURES; TABLE LOOKUP;

CELLS;

EID: 84883472319     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2013.6573676     Document Type: Conference Paper

References (16)

1. -(2011) International Technology Roadmap for Semiconductors. [Online].
2. W. Kim, S. I. Park, Z. Zhang, Y. Yang-Liauw, D. Sekar, H. Wong, and S. Wong, "Forming-free nitrogen-doped AlOX RRAM with sub-uA programming current." in VLSI Technology (VLSIT), 2011 Symposium on, june 2011, pp. 22-23.
3. H. Yoda, S. Fujita, N. Shimomura, E. Kitagawa, K. Abe, K. Nomura, H. Noguchi, and J. Ito, "Progress of stt-mram technology and the effect on normally-off computing systems." in Electron Devices Meeting, 2012. IEDM Technical Digest. IEEE International, dec. 2012.
4. N. Bruchon, "Evaluation, validation and design of hybrid CMOS-non volatile emerging technology cells for dynamically reconfigurable fine grain architecture." PhD thesis, Université Montpellier 2, 2007.
5. S. Min, "Semiconductor flash memory scaling." PhD thesis, University of California Berkeley, 2003
6. K.J. Hass, "Magnetic shadow RAM." IEEE Non Volatile Memory Technology Symp., 2006, pp. 45-48
7. W.J Gallaher, S.S.P "Development of the magnetic tunnel junction MRAM at IBM: from first junctions to a 16-Mb MRAM demonstrator chip," IBMJ. Res. Dev., 2006, 50, pp. 5-23
8. Y. Iba, K. Tsunoda, Y.M. Lee, C. Yoshida, H. Noshiro, A. Takahashi, Y. Yamazaki, M. Nakabayashi, A. Hatada, M. Aoki, T. Sugii, T., "Strain- engineering for high-performance STT-MRAM," VLSI Technology (VLSIT), 2011 Symposium on, vol., no., pp.212,213, 14-16 June 2011
9. N. Sakimura, T. Sugibayashi, R. Nebashi and N. Kasai "Nonvolatile Magnetic Flip-Flop for standby-power free SoCs," IEEE-CICC Conference, pp.355-358, (2008).
10. William C. Black and B. Das. Programmable logic using giantmagnetoresistance and spin-dependent tunneling devices (invited). AIP, 87:6674-6679, 2000.
11. W. Zhao, C. Chappert, V. Javerliac, and J.P. Noziere. "High speed, high stability and low power sensing amplifier for mtj/cmos hybrid logic circuits." IEEE Transactions on Magnetics, 45(10):3784 3787, Oct. 2009.
12. E. Seevinck, F. List, and J. Lohstroh, "Static noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, Oct 1987.
13. V.Javerliac. "Magnetic tunnel junction compact device model for electrical simulations of spintronics components." Magnetism and Magnetic Materials, San Jose, USA, 2005. 70, 95
14. Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, and Guillaume Prenat. "TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA." ACM Trans. Reconfigurable Technol. Syst. 2, 2, Article 8 (June 2009), 19 pages. DOI=10.1145/1534916.1534918
15. G. Di Pendian, K. Torki, G. Prenat, Y., L. Torres. "Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology." PATMOS 2011: 83-91
16. L. Torres, W. Zhao "Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design." ACM Great Lakes Symposium on VLSI 2011: 429-430