A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 296-297

  Kim, Jung Pill ^a   Kim, Taehyun ^a   Hao, Wuyang ^a   Rao, Hari M ^a   Lee, Kangho ^a   Zhu, Xiaochun ^a   Li, Xia ^a   Hsu, Wah ^a   Kang, Seung H ^a   Matt, Nowak ^a   Yu, Nick ^a  

^a QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE SHARING; CMOS PROCESSS; DESIGN FEATURES; DESIGN TECHNIQUE; FAST READ; READ OPERATION; ROW DECODER; SENSING CIRCUITS;

CMOS INTEGRATED CIRCUITS; DESIGN;

VLSI CIRCUITS;

EID: 80052660750     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. G. De Sandre, et al., ISSCC, pp. 268-269, 2010
3. C.J.Lin, et al., IEDM, pp. 279-280, 2009
4. K. Tsuchida, et al., ISSCC, pp. 258-259, 2010
5. D. Gogl, et al., IEEE JSSC, pp. 902-908, April 2005
6. D. Halupka, ISSCC, pp. 256-257, 2010