Glitch power minimization by selective gate freezing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 3, 2000, Pages 287-298

  Benini, Luca ^a,b   De Micheli, Giovanni ^a,c   Macii, Alberto ^a,d   Macii, Enrico ^a,d   Poncino, Massimo ^a,d   Scarsi, Riccardo ^d  

^a IEEE

^b UNIVERSITY OF BOLOGNA   (Italy)

^c STANFORD UNIVERSITY   (United States)

^d POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; LOGIC GATES;

GATE FREEZING; GLITCH POWER MINIMIZATION; POWER OPTIMIZATION;

COMBINATORIAL CIRCUITS;

EID: 0033726476     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.845895     Document Type: Article

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