A 0.33-V, 500-kHz, 3.94-μW 40-nm 72-Kb 9T subthreshold SRAM with ripple bit-line structure and negative bit-line write-assist

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 12, 2012, Pages 863-867

  Lu, Chien Yu ^a   Tu, Ming Hsien ^a,b   Yang, Hao I ^a   Wu, Ya Ping ^a,b   Huang, Huan Shun ^a,b   Lin, Yuh Jiun ^a,b   Lee, Kuen Di ^a,b   Kao, Yung Shin ^a,b   Chuang, Ching Te ^a   Jou, Shyh Jye ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

9T SRAM cell; Negative bit line (NBL); ripple bit line (RPBL); subthreshold static random access memory (SRAM); ultra low voltage

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY;

BIT LINES; BOOSTING EFFICIENCY; HIERARCHICAL BIT LINE; OPERATION FREQUENCY; SRAM CELL; STATIC RANDOM ACCESS MEMORY; TOTAL POWER CONSUMPTION; ULTRA-LOW-VOLTAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 84873375583     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231017     Document Type: Article

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