P-P-N based 10T SRAM cell for low-leakage and resilient subthreshold operation

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 3, 2011, Pages 695-704

  Lo, Cheng Hung ^a   Huang, Shi Yu ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

10T cell; bitline leakage; low leakage; noise margin; PPN; SRAM

Indexed keywords

BITLINE LEAKAGE; LOW-LEAKAGE; NOISE MARGIN; PPN; SRAM; T CELLS;

STATIC RANDOM ACCESS STORAGE;

EID: 79952072363     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2102571     Document Type: Article

References (9)

1. B. Calhoun and A. Chandrakasan, "Static noise margin variation for subthreshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, pp. 1673-1679, 2006. (Pubitemid 44109303)
2. B. H. Calhoun and A. Chandrakasan, "A 256 kb subthreshold SRAM in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680-688, Mar. 2007.
3. T. Kim, J. Liu, J. Keane, and C. Kim, "A 0.2 V, 480 kb sub-threshold SRAM with 1 k cells per bitline for ultra-low-voltage computing," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 518-529, Feb. 2008. (Pubitemid 351190219)
4. B. Zhai, D. Blaauw, and D. Sylvester, "A variation-tolerant sub-200 mV 6-T subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338-2348, Oct. 2008.
5. N. Verma and A. Chandrakasan, "A 256 kb 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
6. T. Kim, J. Liu, and C. Kim, "A voltage scalable 0.26V, 64 kb 8TSRAM with Vmin lowering techniques and deep sleep mode," IEEE J. Solid- State Circuits, vol. 44, no. 6, pp. 1785-1795, Jun. 2009.
7. J. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust Schmitt trigger based subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007. (Pubitemid 47483011)
8. I. J. Chang, J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.
9. M. Sharifkhani and M. Sachdev, "An energy efficient 40 Kb SRAM module with extended read/write noise margin in 0.13 μm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 620-630, Feb. 2009.