A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 4, 2008, Pages 456-465

  Kil, Jonggab ^b   Gu, Jie ^a,c   Kim, Chris H ^a,c  

^a IEEE

^b INTEL CORPORATION   (United States)

^c University of Minnesota   (United States)

Author keywords

Capacitive boosting; Clock distribution network; Global wire delay; Subthreshold circuits

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS; THERMAL EFFECTS; TRANSISTORS;

CAPACITIVE BOOSTING; CLOCK DISTRIBUTION NETWORK; SUBTHRESHOLD CIRCUITS;

INTERCONNECTION NETWORKS;

EID: 41549094625     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.915455     Document Type: Article

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