A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 46-47

  Kushida, Keiichi ^a   Suzuki, Azuma ^a   Fukano, Gou ^a   Kawasumi, Atsushi ^a   Hirabayashi, Osamu ^a   Takeyama, Yasuhisa ^a   Sasaki, Takahiko ^a   Katayama, Akira ^a   Fujimura, Yuuki ^a   Yabe, Tomoaki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

VLSI CIRCUITS;

BIT LINES; FAILURE RATES; HIERARCHICAL BIT LINE; HIGH-DENSITY; LOW SUPPLY VOLTAGES; ORDERS-OF-MAGNITUDE; SENSE AMPLIFIER; TEST CHIPS; WRITE-BACK;

STATIC RANDOM ACCESS STORAGE;

EID: 51949112103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585946     Document Type: Conference Paper

References (4)

1. Y. Morita et al., Dig.Symp. VLSI Circuits, pp. 256-257, Jun 2007.
2. L. Chang et al., Dig.Symp. VLSI Circuits, pp. 252-253, Jun 2007.
3. A. Kawasumi et al., ISSCC Dig. Tech. papers, Feb. 2008.
4. B.Yang et al., JSSC, Vol.40, pp.1366-1376, Jun. 2005.