Ultralow-power design in near-threshold region

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 237-252

  Markovic, Dejan ^a   Wang, Cheng C ^a   Alarcon, Louis P ^b   Liu, Tsung Te ^b   Rabaey, Jan M ^b  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit optimization; CMOS digital integrated circuits; Curve fitting; Design methodology; Integrated circuit design; Integrated circuit modeling; Leakage currents; Logic design; Optimization methods; Pipelines; Sensitivity

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURVE FITTING; DIGITAL INTEGRATED CIRCUITS; ENERGY GAP; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; LOGIC DESIGN; PIPELINES;

CIRCUIT OPTIMIZATION; CMOS DIGITAL INTEGRATED CIRCUITS; DESIGN METHODOLOGY; INTEGRATED CIRCUIT MODELING; OPTIMIZATION METHOD; SENSITIVITY;

COMPUTER CIRCUITS;

EID: 75649141765     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2035453     Document Type: Article

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