Improving power-delay performance of ultra-low-power subthreshold SCL circuits

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 56, Issue 2, 2009, Pages 127-131

  Tajalli, Armin ^a   Alioto, Massimo ^b   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

^b UNIVERSITY OF SIENA   (Italy)

Author keywords

Source coupled logic (SCL); Subthreshold SCL (STSCL); Ultralow power circuits; Weak inversion SCL (WiSCL)

Indexed keywords

BUFFER AMPLIFIERS; COMPUTER CIRCUITS; COUPLED CIRCUITS; DELAY CIRCUITS; EFFICIENCY; EMITTER COUPLED LOGIC CIRCUITS; TIMING CIRCUITS;

ANALYTICAL RESULTS; POWER DELAY PRODUCT; SOURCE COUPLED LOGIC; SUB-THRESHOLD CIRCUITS; SUBTHRESHOLD SCL; SUBTHRESHOLD SCL (STSCL); ULTRA-LOW-POWER CIRCUITS; WEAK INVERSION SCL (WISCL);

LOW POWER ELECTRONICS;

EID: 62749197560     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.2011603     Document Type: Article

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