Silicon surface passivation by thin thermal oxide/PECVD layer stack systems

IEEE Journal of Photovoltaics

Volumn 1, Issue 2, 2011, Pages 135-145

  MacK, Sebastian ^a   Wolf, Andreas ^a   Brosinsky, Christoph ^b   Schmeisser, Simon ^c   Kimmerle, Achim ^a   Saint Cast, Pierre ^a   Hofmann, Marc ^a   Biro, Daniel ^a  

^a FRAUNHOFER INSTITUTE FOR SOLAR ENERGY SYSTEMS ISE   (Germany)

^b Consultant Working in Germany ^*  (Germany)

^c UNIVERSITY OF FREIBURG   (Germany)

Author keywords

Dielectric films; interface states; photovoltaic cells; SiO2

Indexed keywords

ANALYTICAL CALCULATION; CAPACITANCE VOLTAGE MEASUREMENTS; CAPPING LAYER; CHARGE FORMATION; CHEMICAL PASSIVATION; DIELECTRIC CAPPING LAYERS; FIXED CHARGE DENSITY; FLOAT ZONE SILICON; GATE VOLTAGES; INJECTION DENSITY; INTERFACE PARAMETERS; INTERFACE TRAP DENSITY; LAYER STACKS; LAYER THICKNESS; P-TYPE; P-TYPE SILICON; POST-METALLIZATION ANNEALING; SILICON SURFACES; SIO2; SPACE CHARGE REGIONS; SURFACE RECOMBINATION VELOCITIES; THERMAL OXIDES; THIN LAYERS;

DIELECTRIC FILMS; INTERFACE STATES; INTERFACES (MATERIALS); PASSIVATION; PHOTOVOLTAIC CELLS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON NITRIDE;

SILICON OXIDES;

EID: 84865155391     PISSN: 21563381     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPHOTOV.2011.2173299     Document Type: Article

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