A reliable routing architecture and algorithm for NoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 5, 2012, Pages 726-739

  Deorio, Andrew ^a   Fick, David ^a   Bertacco, Valeria ^a   Sylvester, Dennis ^a   Blaauw, David ^a   Hu, Jin ^a   Chen, Gregory ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Fault tolerance; hard faults; networks on chip (NoCs); reconfiguration; reliability; routing algorithms

Indexed keywords

ARCHITECTURAL COMPONENTS; CHIP MULTIPROCESSOR; COMMUNICATION MEDIUM; CRITICAL DIMENSION; DIGITAL DESIGNS; DISTRIBUTED ROUTING ALGORITHM; ENTIRE SYSTEM; FAULT-TOLERANT; FAULTY NODE; GRACEFUL PERFORMANCE DEGRADATIONS; HARD FAULTS; MANY CORE; NETWORKS ON CHIPS; ON CHIP INTERCONNECT; ON-CHIP NETWORKS; PERMANENT FAULTS; RE-CONFIGURABLE; RECONFIGURATION; RELIABLE ROUTING; SCALABLE COMMUNICATION; SINGLE POINT; TRANSISTOR SCALING; TWO-LEVEL APPROACH;

COMMUNICATION; FAULT TOLERANCE; MICROPROCESSOR CHIPS; RELIABILITY; ROUTING ALGORITHMS; TRANSISTORS;

ROUTERS;

EID: 84860290977     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2181509     Document Type: Article

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