An array-based test circuit for fully automated gate dielectric breakdown characterization

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 121-124

  Keane, John ^b   Venkatraman, Shrinivas ^b   Butzen, Paulo ^a   Kim, Chris H ^b  

^a UNIVERSIDADE ESTADUAL DO RIO GRANDE DO SUL   (Brazil)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE DIELECTRIC BREAKDOWNS; GATE RESISTANCES; MEASUREMENT RESULTS; SPATIAL CORRELATIONS; STATISTICAL PROCESSES; TEST ARRAYS; TEST CIRCUITS;

ELECTRIC BREAKDOWN; GATE DIELECTRICS; GATES (TRANSISTOR); INTEGRATED CIRCUITS;

NETWORKS (CIRCUITS);

EID: 57849161523     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672036     Document Type: Conference Paper

References (8)

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8. E. Y. Wu, et al., "Experimental Evidence of TBD Power-Law for Voltage Dependence of Oxide Breakdown in Ultrathin Gate Oxides," Trans. On Electron Devices, vol. 49, no. 12, pp. 2244-2253, 2002.