SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 123-134

  Sorin, Daniel J ^a   Martin, Milo M K ^a   Hill, Mark D ^a   Wood, David A ^a  

^a University of Wisconsin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODING ERRORS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ERROR DETECTION; INTERCONNECTION NETWORKS; SWITCHES;

ERROR CORRECTING CODES (ECC);

PIPELINE PROCESSING SYSTEMS;

EID: 0036292677     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (49)

1. Cache-aided rollback error recovery (CARER) algorithms for shared-memory multiprocessor systems
2. Evaluating non-deterministic multi-threaded commercial workloads
3. An approach to crosstalk effect analyses and avoidance techniques in digital CMOS VLSI circuits
4. DIVA: A reliable substrate for deep submicron microarchitecture design
5. An architecture for tolerating processor failures in shared-memory multiprocessors
6. Generating representative Web workloads for network and server performance evaluation
7. Sequoia: A fault-tolerant tightly coupled multiprocessor for transaction processing
8. Interconnect scaling - The real limiter to high performance
9. Dynamic verification of cache coherence protocols
10. Starfire: Extending the SMP envelope
11. Architectural support for scalable speculative parallelization in shared-memory systems
12. Architecture and implementation of the reliable router
13. A white paper on the benefits of chipkill-correct ECC for PC server main memory
14. Manetho: Transparent rollback-recovery with low overhead, limited rollback, and fast output commit
15. Tightly coupled multiprocessor system speeds memory-access times
16. Spider: A high-speed network interconnect
17. Is SC + ILP = RC?
18. Speculative versioning cache
19. Reining in complexity
20. The fuzzy barrier: A mechanism for high speed synchronization of processors
21. IBM 3081 processor unit: Design considerations and design process
22. A general purpose cache-aided rollback error recovery (CARER) technique
23. Integrity S2: A fault-tolerant UNIX platform
24. The intel 432: A VLSI architecture for fault-tolerant computing
25. Calculation of the soft error rate of Submicron CMOS logic circuits
26. Simics: A full system simulation platform
27. A case for redundant arrays of inexpensive disks (RAID)
28. Diskless checkpointing
29. Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models
30. Transient fault detection via simultaneous multithreading
31. Alpha particles worry IC makers as device features keep shrinking
32. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors
33. Fault-tolerant systems in commercial applications
34. The quality and reliability of intel's quarter micron process
35. IBM S/390 parallel enterprise server G5 fault tolerance: A historical perspective
36. The potential for using thread-level data speculation to facilitate automatic parallelization
37. Slipstream processors: Improving both performance and fault tolerance
38. Increasing work, pushing the clock
39. Checkpointmg and its applications
40. The stratus computer system
41. The SPLASH-2 programs: Characterization and methodological considerations
42. Verifying a multiprocessor cache controller using random test generation
43. Error recovery in shared memory multiprocessors using private caches
44. IBM experiments in soft fails in computer electronics