Reliable communication in systems on chips

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 77-

  De Micheli, Giovanni ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Networking; SoCs; VLSI

Indexed keywords

CROSSTALK; DATA COMMUNICATION SYSTEMS; ENERGY UTILIZATION; INTERCONNECTION NETWORKS; NETWORKS (CIRCUITS); SIGNAL ENCODING; TOPOLOGY; VLSI CIRCUITS;

MEAN TIME TO FAILURE (MTTF); MEMORY ARRAYS; NETWORK TOPOLOGY; SYSTEM ON CHIP (SOC);

MICROPROCESSOR CHIPS;

EID: 4444314731     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996590     Document Type: Conference Paper

References (9)

1. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computers, January 2002, pp. 70-78.
2. D. Bertozzi, L. Benini and G. De Micheli, "Low-Power Error-Resilient Encoding for On-chip Data Busses," DATE Proceedings, Paris, 2002, pp. 102-109.
3. W. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks" DAC Proceedings, pp.684-689, 2001.
4. K. Goossens et al. "Networks on Silicon: Combining Best Efforts and Guaranteed Services," DATE Proceedings, pp. 423-427, 2002.
5. P. Guerrier, A. Grenier, "A Generic Architecture for On-chip Packet-switched Interconnections," DATE Proceedings, pp. 250-256, 2000.
6. A. Jalabert, S. Murali, L. Benini, G.De Micheli, "XpipesCompiler: A Tool for Instantiating Application Specific Networks on Chip," DATE Proceedings, 2004, pp. 884-889.
7. S. Kumar et al. "A Network on Chip Architecture and Design Methodology", IEEE Annual Symposium on VLSI, April 2002, pp. 105-112.
8. F. Worm, P. Ienne, P. Thiran, and G. De Micheli, "An Adaptive Low-power Transmission Scheme for On-chip Networks," ISSS Proceedings, 2002.
9. T. Ye, L. Benini and G. De Micheli, " Packetization and Routing Analysis of On-chip Multiprocessor Networks," Journal of System Architecture, 2004.