A resilient on-chip router design through data path salvaging

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 437-442

  Liu, Cheng ^a   Zhang, Lei ^a   Han, Yinhe ^a   Li, Xiaowei ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PATHS; ENTIRE SYSTEM; FAULT RATES; FAULT-TOLERANT; GRACEFUL PERFORMANCE DEGRADATIONS; HARDWARE OVERHEADS; HIGH RELIABILITY; INPUT BUFFERS; MANUFACTURING DEFECTS; NANO-METER REGIMES; NETWORK ON CHIP; ON CHIP COMMUNICATION; ON CHIPS; PERMANENT FAULTS; ROUTER DESIGN; TECHNOLOGY ADVANCES; VERY LARGE SCALE INTEGRATED CIRCUIT;

COMPUTER AIDED DESIGN; NETWORKS (CIRCUITS); QUALITY ASSURANCE; REDUNDANCY; SALVAGING; VLSI CIRCUITS;

ROUTERS;

EID: 79952974640     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722230     Document Type: Conference Paper

References (22)

1. W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Design Automation Conference, 2001. Proceedings, pp. 684-689, 2001.
2. S. Borkar et al., "Microarchitecture and design challenges for gigascale integration," in Keynote. In Proceedings of the 37th International Symposium on Microarchitecture (MICRO-37), 2004.
3. L. Benini and G. De Micheli, Networks on chips: technology and tools. Morgan Kaufmann Pub, 2006.
4. C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE micro, vol. 23, no. 4, pp. 14-19, 2003.
5. S. Borkar, "Designing reliable systems from unreliable components: the challenges of transistor variability and degradation," IEEE Micro, vol. 25, no. 6, pp. 10-16, 2005.
6. B. Paul, D. Tudor, and M. Radu, "Stochastic communication: A new paradigm for fault-tolerant networks-on-chip," VLSI Design, vol. 2007, 2007.
7. M. Pirretti, G. Link, R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. Irwin, "Fault tolerant algorithms for network-on-chip interconnect," in IEEE Computer society Annual Symposium on VLSI, 2004. Proceedings, pp. 46-51, 2004.
8. F. Angiolini, D. Atienza, S. Murali, L. Benini, and G. De Micheli, "Reliability support for on-chip memories using networks-on-chip," in Computer Design, 2006. ICCD 2006. International Conference on, pp. 389-396, 2007.
9. R. Boppana and S. Chalasani, "Fault-tolerant routing with non-adaptive wormhole algorithms inmesh networks," in Supercomputing'94. Proceedings, pp. 693-702, 1994.
10. D. Siewiorek and R. Swarz, Reliable computer systems: design and evaluation. AK Peters, Ltd., 1998.
11. J. Smolens, B. Gold, J. Kim, B. Falsafi, J. Hoe, and A. Nowatzyk, "Fingerprinting: bounding soft-error detection latency and bandwidth," in Proceedings of the 11 th international conference on Architectural support for programming languages and operating systems: Boston, MA, USA, 2004.
12. C. Weaver and T. Austin, "A fault tolerant approach to microprocessor design," in Proceedings of the International Conference on Dependable Systems and Networks, pp. 411-420, Citeseer, 2001.
13. K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, "Bulletproof: A defect-tolerant CMP switch architecture," in High-Performance Computer Architecture, 2006. The Twelfth International Symposium on, pp. 5-16, 2006.
14. L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," Computer, vol. 35, no. 1, pp. 70-78, 2002.
15. T. Lehtonen, P. Liljeberg, and J. Plosila, "Fault tolerance analysis of NoC architectures," in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, pp. 361-364, 2007.
16. M. Koibuchi, H. Matsutani, H. Amano, and T. Pinkston, "A lightweight fault-tolerant mechanism for Network-on-Chip," in Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, pp. 13-22, IEEE Computer Society, 2008.
17. D. Fick, A. DeOrio, J. Hu, V. Bertacco, D. Blaauw, and D. Sylvester, "Vicis: a reliable network for unreliable silicon," in Proceedings of the 46th Annual Design Automation Conference, pp. 812-817, ACM, 2009.
18. M. Palesi, S. Kumar, and V. Catania, "Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 426 -440, march 2010.
19. A. Alaghi, N. Karimi, M. Sedghi, and Z. Navabi, "Online NoC switch fault detection and diagnosis using a high level fault model," in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, 2007. DFT'07, pp. 21-29, 2007.
20. D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw, "A highly resilient routing algorithm for fault-tolerant NoCs," in Proc. DATE, 2009.
21. M. Gomez, J. Duato, J. Flich, P. Lopez, A. Robles, N. Nordbotten, O. Lysne, and T. Skeie, "An efficient fault-tolerant routing methodology for meshes and tori," Computer Architecture Letters, vol. 3, no. 1, pp. 3-3, 2004.
22. C. Ho and L. Stockmeyer, "A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers," IEEE Transactions on Computers, vol. 53, no. 4, pp. 427-438, 2004.