Architecture and Synthesis for On-Chip Multicycle Communication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 4, 2004, Pages 550-564

  Cong, Jason ^a   Fan, Yiping ^a   Han, Guoling ^a   Yang, Xun ^a,b   Zhang, Zhiru ^a  

^a University of California   (United States)

^b Silvaco Data Systems Inc   (United States)

Author keywords

Binding; High level synthesis; Interconnect; Multicycle communication; Placement; Scheduling

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTATIONAL METHODS; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; PRODUCT DESIGN; SCHEDULING; TRANSISTORS;

HIGH-LEVEL SYNTHESIS; INTERCONNECTS; MULTICYCLE COMMUNICATION; PLACEMENT;

NANOTECHNOLOGY;

EID: 2342420709     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.825872     Document Type: Conference Paper

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