Congestion-aware logic synthesis

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 664-671

  Pandini, Davide ^a   Pileggi, Lawrence T ^b   Strojwas, Andrzej J ^b  

^a STMICROELECTRONICS   (Italy)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONGESTION MINIMIZATION; DEEP SUB-MICRON TECHNOLOGY; GATE CAPACITANCE; INDUSTRIAL CIRCUITS; INTERCONNECT EFFECTS; NOVEL METHODOLOGY; WIRING CAPACITANCE; WIRING CONGESTION;

CAPACITANCE; EXHIBITIONS; INTEGRATED CIRCUITS;

LOGIC DESIGN;

EID: 84893749837     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998370     Document Type: Conference Paper

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