Automatic memory partitioning and scheduling for throughput and power optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 697-704

  Cong, Jason ^a,b   Jiang, Wei ^a   Liu, Bin ^a   Zou, Yi ^a  

^a Engineering IV   (United States)

^b AutoESL Design Technologies Inc   (United States)

Author keywords

Behavioral synthesis; Memory partition

Indexed keywords

BANDWIDTH; CACHE MEMORY; EMBEDDED SOFTWARE; ENERGY UTILIZATION; HIGH LEVEL SYNTHESIS; POLYNOMIAL APPROXIMATION; SCHEDULING;

BEHAVIORAL SYNTHESIS; DYNAMIC POWER CONSUMPTION; MODERN EMBEDDED SYSTEMS; REDUCE ENERGY CONSUMPTION; SCHEDULING INFORMATION; STATE-OF-THE-ART TECHNIQUES; THROUGHPUT CONSTRAINTS; THROUGHPUT IMPROVEMENT;

SYSTEMS ANALYSIS;

EID: 76349122658     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687528     Document Type: Conference Paper

References (18)

1. A. Agarwal, D. Kranz, and V. Natarajan. Automatic partitioning of parallel loops and data arrays for distributed shared-memory multiprocessors. IEEE Trans. Parallel Distributed Systems, 6:943-962, 1995.
2. J. M. Anderson and M. S. Lam. Global optimizations for parallelism and locality on scalable parallel machines. In In Proc. of the SIGPLAN PLDI'93, pages 112-125, 1993.
3. N. Baradaran and P. C. Diniz. A compiler approach to managing storage and memory bandwidth in configurable architectures. ACM Trans. Des. Autom. Electron. Syst., 13(4):1-26, 2008.
4. I. M. Bomze, M. Budinich, P. M. Pardalos, and M. Pelillo. The maximum clique problem. In Handbook of Combinatorial Optimization, pages 1-74. Kluwer Academic Publishers, 1999.
5. J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang. Platform-based behavior-level and system-level synthesis. In Proceedings of IEEE SOCC, 2006.
6. J. Cong and Y. Zou. Lithographic aerial image simulation with FPGA-based hardware acceleration. In Proc. of international symposium on Field programmable gate arrays, 2008.
7. W. Gong, G. Wang, and R. Kastner. Storage assignment during high-level synthesis for con.gurable architectures. In Proc. of ICCAD '05.
8. http://www.magam-da.com. Magma Website.
9. http://www.tsmc.com. TSMC Website.
10. http://www.xilinx.com. Xilinx Website.
11. K. Kennedy and J. R. Allen. Optimizing compilers for modern architectures: a dependence-based approach. Morgan Kaufmann Publishers Inc., 2002.
12. C.-G. Lyuh and T. Kim. Memory access scheduling and binding considering energy minimization in multi-bank memory systems. In Proc. of DAC '04.
13. M. Poncino, L. Benini, and A. Macii. A recursive algorithm for low-power memory partitioning. In Proc. of IEEE/ACM International Symposium on Low Power Electronics and Design, pages 78-83, 2000.
14. J. Ramanujam and P. Sadayappan. Compile-time techniques for data distribution in distributed memory machines. IEEE Trans. Parallel Distrib. Syst., 2(4):472-482, 1991.
15. B. R. Rau. Iterative modulo scheduling: an algorithm for software pipelining loops. In Proceedings of the 27th annual international symposium on Microarchitecture, 1994.
16. Y. Tatsumi and H. Mattausch. Fast quadratic increase of multiport-storage-cell area with port number. Electronics Letters, 35(25):2185-2187, Dec 1999.
17. S. Verdoolaege, R. Seghir, K. Beyls, V. Loechner, and M. Bruynooghe. Counting integer points in parametric polytopes using barvinok's rational functions. Algorithmica, 48(1):37-66, 2007.
18. Z. Wang and X. S. Hu. Power aware variable partitioning and instruction scheduling for multiple memory banks. In Proc. of DATE '04.