A metric for layout-friendly microarchitecture optimization in high-level synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 1239-1244

  Cong, Jason ^a   Liu, Bin ^a  

^a Engineering IV   (United States)

Author keywords

high level synthesis; interconnect; layout

Indexed keywords

EFFICIENT ESTIMATION; HIGH LEVEL SYNTHESIS; INTERCONNECT; INTERCONNECT STRUCTURES; LAYOUT; LAYOUT-FRIENDLY; MICRO ARCHITECTURES; NETLIST; NETLIST STRUCTURE; SEMIDEFINITE PROGRAMMING RELAXATIONS; TEST CASE;

COMPUTER AIDED DESIGN; MATHEMATICAL PROGRAMMING;

COMPUTER ARCHITECTURE;

EID: 84863553659     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228587     Document Type: Conference Paper

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