Platform-based behavior-level and system-level synthesis

2006 IEEE International Systems-on-Chip Conference, SOC

Volumn , Issue , 2006, Pages 199-202

  Cong, Jason ^a   Fan, Yiping ^a   Han, Guoling ^a   Jiang, Wei ^a   Zhang, Zhiru ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTER HARDWARE; COMPUTER SOFTWARE; ELECTRONIC EQUIPMENT; LOGIC DESIGN; SPECIFICATIONS;

ELECTRONIC DESIGN AUTOMATION (EDA); SYSTEM-LEVEL SYNTHESIS; SYSTEM-ON-A-CHIP (SOC) DESIGN;

MICROPROCESSOR CHIPS;

EID: 43749087793     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2006.283880     Document Type: Conference Paper

References (8)

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2. J. Cong and Y. Fan. Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture, to appear in Proc. International Conference on Computer-Aided Design, 2006.
3. J. Cong, Y. Fan, G. Han, and Z. Zhang, Application-Specific Instruction Generation for Configurable Processor Architectures. In Proc. International Symposium on FPGAs, pages 183-189, 2004.
4. J. Cong and Z. Zhang. An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation. In Proc. Design Automation Conference, 2006.
5. S. Gupta, R. Gupta, N. Dutt, and A. Nicolau. SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits. Springer, May 2004.
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7. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2005 Edition.
8. K. Wakabayashi. C-Based Behavioral Synthesis and Verification Analysis on Industrial Design Examples. In Proc. ASPDAC, pages 344-348, Jan. 2004.