Compatibility path based binding algorithm for interconnect reduction in high level synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 435-441

  Kim, Taemin ^a   Liu, Xun ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; BENCHMARK PROGRAMS; BINDING ALGORITHM; COMPATIBILITY GRAPH; COMPUTER-AIDED DESIGN; FUNCTIONAL UNIT; GLOBAL INTERCONNECTS; HIGH-LEVEL SYNTHESIS; INTERCONNECT COMPLEXITY; INTERCONNECT REDUCTION; INTERNATIONAL CONFERENCES; LONG-PATH; MULTIPLE INPUTS; OPERATION VARIABLES; TOTAL WIRE LENGTH; VERILOG; WEIGHTED BIPARTITE MATCHING;

CHLORINE COMPOUNDS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL GEOMETRY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DESIGN; GRAPH THEORY; MATLAB; MULTIPLEXING; MULTIPLEXING EQUIPMENT;

ALGORITHMS;

EID: 50249184821     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397304     Document Type: Conference Paper

References (27)

1. I. Ahmad and C. Y. R. Chen. Post-processor for data path synthesis using multiport memories. In Proceedings of ICCAD, November 1991.
2. H. A. Atat and I. Ouaiss. Register binding for fpgas with embedded memory. In Proceedings of FCCM, April. 2004.
3. A. Avakian and I. Ouaiss. Optimizing register binding in fpgas using simulated annealing. In Proceedings of ReConFig, September 2005.
4. D. Chen and J. Cong. Register binding and port assignment for multiplexer optimization. In Proceedings of ASPDAC, January 2004.
5. D. Chen, J. Cong, and Y. Fan. Low-power high-level synthesis for fpga architectures. In Proceedings of ISLPED, August 2003.
6. J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang. Architecture and synthesis for on-chip multicycle communication. IEEE Transactions on CAD of integrated circuits and systems, 2004.
7. J. Cong, Y. Fan, and W. Jian. Platform-based resource binding using a distributed register-file microarchitecture. In Proceedings of ICCAD, November 2006.
8. J. Cong, Y. Fan, X. Yang, and Z. Zhang. Architecture and synthesis for multi-cycle communication.. In Proceedings of ISPD, April 2003.
9. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. INTRODUCTION TO ALGORlTHMS,2nd Edition. The MIT Press, 2001.
10. D. Gajski, A. Wu, N. Dutt, and S. Lin. HIGH-LEVEL SYNTHESIS. Jntroduction to Chip and System Design. Kluwer Academic Publishers, 1992.
11. C.-Y. Huang, Y.-S. Chen, Y.-L. Lin, and Y.-C. Hsu. Data path allocation based on bipartite weighted matching. In Proceedings of DAC, June 1990.
12. A. Kaplan, P. Brisk, and R. Kastner. Data communication estimation and reduction for reconfigurable systems. In Proceedings of DAC, June 2003.
13. R. Kastner, W. Gong, X. Hao, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh. Layout driven data communication optimization for high level synthesis. In Proceedings of DATE, March 2006.
14. D. Kim, J. Jung, S. Lee, J. Jeon, and K. Choi. Behavior-to-placed rtl synthesis with performance-driven placement. In Proceedings of ICCAD, November 2001.
15. T. Kim and C. L. Liu. Utilization of multiport memories in data path synthesis. In Proceedings of DAC, June 1993.
16. T. Kim and C. L. Liu. An integrated data path synthesis algorithm based on network flow method. In Proceedings of CICC, May 1995.
17. F. J. Kurdahi and A. C. Parker. Real:a program for register allocation. In Proceedings of DAC, June 1987.
18. X. Liu and M. C. Papaefthymiou. Design of a 20-mb/s 256-state viterbi decoder. IEEE Transactions on VLSI Systems, 2003.
19. R. Mehra, L. M. Guerra, and J. M. Rabaey. Low-power architectural. synthesis and the impact of exploiting locality. Journal of VLSI Signal Processing, 1996.
20. R. Mehra, L. M. Guerra, and J. M. Rabaey. A partitioning scheme for optimizing interconnect power. IEEE Journal of Solid-State Circuits, 1997.
21. G. D. Micheli. SYNTHESIS AND OPTIMIZATION OF DIGITAL CIRCUITS. McGraw Hill, 1994.
22. C. A. Papachristou and H.Konuk. A linear program, driven scheduling and allocation method followed by an interconnect optimization algorithm. In Proceedings of DAC, June 1990.
23. M. Rim, R. Jain, and R. D. Leone. Optimal, allocation and binding in high-level synthesis. In Proceedings of DAC, June 1992.
24. M. B. Srivastava and M. Potkonjak. Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput. IEEE Transactions on VLSI Systems, .1995.
25. L. Stok. Interconnect optimization during data path allocation. In Proceedings of EURO-DAC, September 1990.
26. J. Um, J. noon Kim, and T. Kim. Layout-driven resource sharing in high-level synthesis. In Proceedings of ICCAD, November 2002.
27. J.-P. Weng and A. C. Parker. 3d scheduling:high-level synthesis with floorplanning. In Proceedings of DAC, June 1991.