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Volumn 2, Issue 4, 1997, Pages 312-343

Layout-driven RTL binding techniques for high-level synthesis using accurate estimators

Author keywords

Algorithms; Binding; Design; Experimentation; Floorplan; FPGAs; High level synthesis; Measurement; Performance

Indexed keywords


EID: 0000132111     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/268424.268425     Document Type: Article
Times cited : (29)

References (35)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.