Measurements for structural logic synthesis optimizations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 6, 2003, Pages 665-674

  Kudva, Prabhakar ^a   Sullivan, Andrew ^b   Dougherty, William ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

Circuit synthesis; Estimation; Logic design; Routing

Indexed keywords

ALGORITHMS; LOGIC CIRCUITS; OPTIMIZATION; PROBLEM SOLVING;

CIRCUIT SYNTHESIS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0038042054     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.811456     Document Type: Conference Paper

References (31)

1. C. Alpert, J. H. Huang, and A. B. Kahng, "Multilevel circuit partitioning," IEEE Trans. Computer-Aided Design, vol. 17, pp. 655-667, Aug. 1998.
2. S. R. Arikati, S. Chaudhuri, and C. D. Zaroliagis, "All-pairs min-cut in sparse networks," Max-Planck-Institut für Informatik, Saarbrücken, Germany, Res. Rep. MPI-I-96-1-007, Mar. 1996.
3. G. D. Battista, P. Eades, R. Tamassia, and I. G. Tollis, Graph Drawing: Algorithms for the Visualization of Graphs. Englewood Cliffs, NJ: Prentice-Hall, 1999.
4. R. Bryant, K. Cheng, A. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey, and A. Sangiovanni-Vincentelli, "Limitations and challenges of computer-aided design technology for CMOS VLSI," Proc. IEEE, vol. 89, pp. 341-366, Mar. 2001.
5. C.-W. Chang, C.-K. Cheng, P. Suaris, and M. Marek-Sadowska, "Fast post-placement rewiring using easily detectable functional symmetries," in Proc. ACM/IEEE Design Automation Conf., June 2000.
6. W. E. Donath, "Equivalence of memory to random logic," IBM J. Res. Develop., pp. 401-407, 1974.
7. Z. Galil, G. F. Italiano, and N. Sarnak, "Fully dynamic planarity testing with applications," J. Assoc. Comput. Mach., vol. 46, no. 1, pp. 28-91, 1999.
8. A. V. Goldberg, P. W. Goldberg, P. A. Pevzner, S. C. Sahinalp, E. Sweedyk, and K. Tsioutsiouliklis, "Cut tree algorithms," in Proc. Symp. Discrete Algorithms, 1999, pp. 376-385.
9. W. Gosti, R. Brayton, and A. Sangiovanni-Vincentelli, "Wire planning in logic synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 1998, pp. 26-33.
10. F. Harary, Graph Theory. Reading, MA: Addison-Wesley, 1969.
11. H. T. Heineken and W. Maly, "Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs," in Proc. Int. Conf. Computer-Aided Design, Nov. 1996, pp. 368-373.
12. G. Karypis and A. Kumar, "Multilevel hypergraph partitioning: application in vlsi domain," in Proc. ACM/IEEE Design Automation Conf., June 1997.
13. R. Krenz, E. Dubrova, and A. Kuehlmann, "Circuit-based evaluation of the arithmetic transform of boolean functions," in Proc. Int. Workshop Logic Synthesis, Mar. 2002.
14. T. Kutzschebauch and L. Stok, "Regularity driven logic synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 2000, pp. 439-446.
15. _, "Congestion aware logic synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 2001, pp. 216-223.
16. T. Lengauer and R. E. Tarjan, "A fast algorithm for finding dominators in a flowgraph," ACM Trans. Program. Lang. Syst., vol. 1, no. 1, pp. 121-141, 1979.
17. A. Liebers, "Planarizing graphs - a survey and annotated bibliography," J. Graph Algorithms Applicat., vol. 5, no. 1, pp. 1-74, 2001.
18. K. Mehlhorn, P. Mutzel, and S. Näher, "An implementation of the hopcroft and tarjan planarity test," Max-Planck-Institut für Informatik, Saarbrücken, Germany, Tech. Rep. MPI-I-93-151, 1993.
19. F. Mo and R. Brayton, "Regular fabrics in deep sub-micron integrated-circuit design," in Proc. Int. Workshop Logic Synthesis, Mar. 2002.
20. J. Moody and D. R. White, "Social cohesion and embeddedness: a hierarchical conception of social groups," Sociolog. Method., 2002.
21. P. Abouzeid, K. Sakouti, G. Saucier, and F. Poirot, "Layout driven logic restructuring/decomposition," in Proc. ACM/IEEE Design Automation Conf., Nov. 1990, pp. 365-368.
22. M. Pedram and N. Bhat, "Layout driven logic restructuring/decomposition," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 134-137.
23. G. Ramalingam and T. Reps, "An incremental algorithm for maintaining the dominator tree of a reducible flow graph," in Proc. Annu. ACM Symp. Principles Program. Lang., 1994, pp. 287-298.
24. R. E. Gomory and T. C. Hu, "Multi-terminal network flows," J. Soc. Ind. Appl. Math., vol. 9, pp. 551-570, 1961.
25. L. Stok, D. Kung, D. Brand, A. D. Drum, A. J. Sullivan, L. N. Reddy, N. Hieter, D. J. Geiger, H. Chao, and P. J. Osier, "Booledozer: Logic synthesis for asics," IBM. J. Res. Develop., vol. 40, no. 4, pp. 407-430, 2001.
26. H. Tangmunarunkit, R. Govindan, S. Jamin, S. Shenker, and W. Willinger, "Network topology generators: degree-based vs structural," in Proc. ACM SIGCOMM, Aug. 2002.
27. T. C. Hu, "Optimum communication spanning trees," J. Soc. Ind. Appl. Math., vol. 3, no. 3, pp. 188-195, 1974.
28. J. Vasudevamurthy and J. Rajski, "A method for concurrent decomposition and factorization of boolean expressions," in Proc. Int. Conf. Computer-Aided Design, Nov. 1990, pp. 510-513.
29. D. R. White and F. Harary, "The cohesiveness of blocks in social networks: node connectivity and conditional density," Sociolog. Method., vol. 31, no. 1, pp. 305-359, 2001.
30. D. R. White and M. Newman, "Fast approximation algorithms for finding node-independent paths in networks," Santa Fe Inst., Santa Fe, NM, Res. Rep. 01-07-035, Mar. 2001.
31. X. Yang, R. Kastner, and M. Sarrafzadeh, "Congestion reduction during placement based on integer programming," in Proc. Int. Conf. Computer-Aided Design, 2001, pp. 573-576.