Congestion aware layout driven logic synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 216-223

  Kutzschebauch, T ^a   Stok, L ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MICROELECTRONICS; VLSI CIRCUITS;

MAPPING ALGORITHMS; PARTIONING ALGORITMS;

LOGIC DESIGN;

EID: 0035208989     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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13. Booledozer: Logic synthesis for ASICs
14. Wavefront technology mapping