Platform-based resource binding using a distributed register-file microarchitecture

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 709-715

  Cong, Jason ^a   Fan, Yiping ^a   Jiang, Wei ^a  

^a University of California   (United States)

Author keywords

Behavior synthesis; Distributed register file; Resource binding

Indexed keywords

DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; LANDFORMS; MICROPROCESSOR CHIPS; REDUCTION; TELECOMMUNICATION;

AREA REDUCTION; BEHAVIOR SYNTHESIS; BINDING ALGORITHM; COMPUTER-AIDED DESIGN; CONNECTIONS (STRUCTURAL); DIRECT OPTIMIZATION; DISTRIBUTED REGISTER-FILE MICROARCHITECTURE (DRFM); EMBEDDED MEMORY BLOCKS; EXPERIMENTAL RESULTS; FUNCTIONAL UNIT (FU); GLOBAL INTERCONNECTS; INTELLECTUAL PROPERTY BLOCK (IP BLOCK); INTERNATIONAL CONFERENCES; MULTIPLEXORS (MUXES); ON CHIP MEMORIES; PERFORMANCE IMPROVEMENTS; REGISTER FILES; REGISTER-TRANSFER LEVEL (RTL); RESOURCE BINDING; SYNTHESIS ALGORITHMS; XILINX VIRTEX II FPGA;

OPTIMIZATION;

EID: 34547302203     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320017     Document Type: Conference Paper

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