'Timing Closure by Design,' a high frequency microprocessor design methodology

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 712-717

  Posluszny, S ^a   Aoki, N ^a   Boerstler, D ^a   Coulman, P ^a   Dhong, S ^a   Flachs, B ^a   Hofstee, P ^a   Kojima, N ^a   Kwon, O ^a   Lee, K ^a   Meltzer, D ^a   Nowka, K ^a   Park, J ^a   Peter, J ^a   Silberman, J ^a   et al , ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION;

CHIP INTEGRATION; DYNAMIC CIRCUITS; TIMING ANALYSIS; TIMING CLOSURE;

COMPUTER AIDED DESIGN;

EID: 0033719810     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/337292.337749     Document Type: Conference Paper

References (7)