High-level synthesis for FPGAs: From prototyping to deployment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 4, 2011, Pages 473-491

  Cong, Jason ^a,b   Liu, Bin ^a,b   Neuendorffer, Stephen ^c   Noguera, Juanjo ^c   Vissers, Kees ^c   Zhang, Zhiru ^a  

^a AutoESL Design Technologies Inc   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c XILINX INC   (United States)

Author keywords

Domain specific design; field programmable gate array (FPGA); high level synthesis (HLS); quality of results (QoR)

Indexed keywords

COMPILATION TECHNOLOGY; DESIGN COMMUNITY; DESIGN PRODUCTIVITY; DOMAIN SPECIFIC; FPGA SYNTHESIS; HIGH-LEVEL SYNTHESIS; HIGH-LEVEL SYNTHESIS (HLS); IMPLEMENTATION PLATFORMS; INDUSTRIAL DESIGN; LEVEL OF ABSTRACTION; MANUAL DESIGN; MULTIPLE APPLICATIONS; PROTOTYPING; QUALITY OF RESULTS (QOR); REGISTER TRANSFER LEVEL; RESOURCE USAGE; SPHERE DECODERS; SYSTEM LEVELS; SYSTEM ON CHIP DESIGN; TIPPING POINT;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; SPHERES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79953076698     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2110592     Document Type: Conference Paper

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