High-level synthesis: A retrospective

High-Level Synthesis: From Algorithm to Digital Circuit

Volumn , Issue , 2008, Pages 13-28

  Gupta, Rajesh ^a   Brewer, Forrest ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

Author keywords

Architectural synthesis; Behavioral synthesis; Hardware modeling; High level synthesis; Resource allocation and binding; Scheduling

Indexed keywords

EID: 77949901514     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4020-8588-8_2     Document Type: Chapter

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