Physical and electrical analysis of post-HfO 2 fluorine plasma treatment for the improvement of In 0.53Ga 0.47As MOSFETs' performance

IEEE Transactions on Electron Devices

Volumn 59, Issue 1, 2012, Pages 139-144

  Chen, Yen Ting ^a   Wang, Yanzhen ^a   Xue, Fei ^a   Zhou, Fei ^a   Lee, Jack C ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Fluorine plasma treatment; HfO 2; high k dielectrics; InGaAs

Indexed keywords

BORDER TRAPS; CAPACITANCE VOLTAGE CHARACTERISTIC; CHANNEL LENGTH; CHANNEL MOBILITY; DRIVE CURRENTS; ELECTRICAL ANALYSIS; ELECTRICAL PERFORMANCE; EQUIVALENT OXIDE THICKNESS; FLUORINE PLASMA; FREQUENCY DISPERSION; GATE STACKS; HFO 2; HIGH-K DIELECTRIC; INGAAS; INTERFACE PASSIVATION; INTERFACE QUALITY; INTERFACE TRAP DENSITY; MOSFETS; SUBTHRESHOLD SWING;

DIELECTRIC MATERIALS; FLUORINE; GALLIUM; PLASMA APPLICATIONS; PLASMAS;

HAFNIUM OXIDES;

EID: 84855462351     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2172687     Document Type: Article

References (36)

1. Y. Xuan, Y. Wu, and P. Ye, "High-performance inversion-type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm," IEEE Electron Device Lett., vol. 29, no. 4, pp. 294-296, Apr. 2008. (Pubitemid 351486762)
2. 2 and HfAlO as gate dielectrics," in IEDM Tech. Dig., 2007, pp. 637-640.
3. 0.47As MOSFETs (EOT ≈ 10 Å) using various interfacial dielectric layers," in Proc. IEEE 67th Device Res. Conf. Dig., 2009, pp. 89-90.
4. 3 gate dielectric," Appl. Phys. Lett., vol. 91, no. 6, p. 063 501, Aug. 2007.
5. 0.47As MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 5, pp. 973-979, May 2010.
6. 2 and silicon passivation layer with equivalent oxide thickness of 18 Å," Appl. Phys. Lett., vol. 94, no. 21, p. 213 505, May 2009.
7. B. Shin, J. R. Weber, R. D. Long, P. K. Hurley, C. G. Van de Walle, and P. C. McIntyre, "Origin and passivation of fixed charge in atomic layer deposited aluminum oxide gate insulators on chemically treated InGaAs substrates," Appl. Phys. Lett., vol. 96, no. 15, p. 152-908, Apr. 2010.
8. D. J. DiMaria and J. W. Stasiak, "Trap creation in silicon dioxide produced by hot electrons," J. Appl. Phys., vol. 65, no. 6, pp. 2342-2356, Mar. 1989.
9. D. J. DiMaria, E. Cartier, and D. Arnold, "Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon," J. Appl. Phys., vol. 73, no. 7, pp. 3367-3384, Apr. 1993.
10. 2 gate stacks by remote RF hydrogen and deuterium plasma treatment," Thin Solid Films, vol. 517, no. 1, pp. 207-208, Nov. 2008.
11. 2-based hole channel field-effect transistors," Appl. Phys. Lett., vol. 85, no. 11, pp. 2101-2103, Sep. 2004.
12. CRC Press, CRC Handbook of Physics and Chemistry, 84th ed, Boca Raton, FL, 2003.
13. 4 plasma passivation," in IEDM Tech. Dig., 2008, pp. 405-408.
14. 2) reliability by incorporation of fluorine," IEEE Electron Device Lett., vol. 27, no. 10, pp. 821-823, Oct. 2006.
15. 2 surface passivation," Appl. Phys. Lett., vol. 93, no. 7, p. 073 504, Aug. 2008.
16. 0.47As n-MOSFETs," Electrochem. SolidState Lett., vol. 13, no. 12, pp. H440-H442, Sep. 2010.
17. 0.47As metal-oxide-semiconductor field-effect transistors by fluorine incorporation," Appl. Phys. Lett., vol. 95, no. 1, p. 013 501, May 2009.
18. 3 gate dielectrics," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 27, no. 4, pp. 2024-2027, Jul. 2009.
19. S. Lee and J.-W. Park, "Effect of fluorine on dielectric properties of SiOF films," J. Appl. Phys., vol. 80, no. 9, pp. 5260-5263, Nov. 1996. (Pubitemid 126586251)
20. 2/SiON gate stacks on nMOSFET," IEEE Electron Device Lett., vol. 31, no. 11, pp. 1178-1180, Nov. 2010.
21. J. Robertson, "Interface states model for III-V oxide interfaces," Microelectron. Eng., vol. 86, no. 7-9, pp. 1558-1560, Jul.-Sep. 2009.
22. R. Xie, T. H. Phung, W. He, Z. Sun, M. Yu, Z. Cheng, and C. Zhu, "High mobility high-k/Ge pMOSFETs with 1 nm EOT - New concept on interface engineering and interface characterization," in IEDM Tech. Dig., 2008, pp. 393-396.
23. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. Dekeersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 42-53, Jan. 1984. (Pubitemid 14561846)
24. 0.47As metal-oxide-semiconductor capacitors," Appl. Phys. Lett., vol. 98, no. 14, p. 142-901, Apr. 2011.
25. 2 oxides," Appl. Phys. Lett., vol. 95, no. 25, p. 253 501, Dec. 2009.
26. 2 gate stack," in IEDM Tech. Dig., 2009, pp. 335-338.
27. 3 gate dielectric," Appl. Phys. Lett., vol. 91, no. 9, p. 093 509, Aug. 2007.
28. 0.47As: Passivation and energy-band parameters," Appl. Phys. Lett., vol. 92, no. 7, p. 072901, Feb. 2008.
29. 3 based ALD dielectric," in Proc. IEEE 69th Device Res. Conf. Dig., 2011, pp. 117-118.
30. 2/TaN gates stack," in IEDM Tech. Dig., 2008, pp. 401-404.
31. 0.47As, " Appl. Phys. Lett., vol. 93, no. 20, p. 202903, Nov. 2008.
32. H. Zhao, N. Kong, Y Chen, Y Wang, F. Xue, F Zhou, S. K. Banerjee, and J. C. Lee, "Effects of InP barrier layer thicknesses and different ALD oxides on device performance of In0.7Ga0.3As MOSFETs," in Proc. IEEE 68th Device Res. Conf. Dig., 2010, pp. 55-56.
33. 3-InGaAs MOS devices," IEEE Electron Device Lett., vol. 32, no. 4, pp. 485-487, Apr. 2011.
34. F Xue, H. Zhao, Y.-T. Chen, Y Wang, F Zhou, and J. C. Lee, "Effect of indium concentration on InGaAs channel metal-oxide-semiconductor field-effect transistors with atomic layer deposited gate dielectric," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 29, no. 4, p. 040601, Jul./Aug. 2011.
35. D. Kuzum, J.-H. Park, T. Krishnamohan, H.-S. P. Wong, and K. C. Saraswat, "The effect of donor/acceptor nature of interface traps on Ge MOSFET characteristics," IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1015-1022, Apr. 2011.
36. Y Q. Wu, M. Xu, R. S. Wang, O. Koybasi, and P. D. Ye, "High performance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/μm: New HBr pretreatment and channel engineering," in IEDM Tech. Dig., 2009, pp. 323-326.