Effects of InP barrier layer thicknesses and different ALD oxides on device performance of In0.7Ga0.3As MOSFETs

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2010, Pages 55-56

  Zhao, Han ^a   Kong, Ning ^a   Chen, Yen Ting ^a   Wang, Yanzhen ^a   Xue, Fei ^a   Zhou, Fei ^a   Banerjee, Sanjay K ^a   Lee, Jack C ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER LAYERS; BI-LAYER; BURIED CHANNELS; CHANNEL MOBILITY; DEVICE CHARACTERISTICS; DEVICE PERFORMANCE; GATE OXIDE; GATE-LEAKAGE CURRENT; HIGH ELECTRON MOBILITY; INALAS; INP; INTERFACE QUALITY; MOSFETS; OXIDE THICKNESS; SUBTHRESHOLD SWING; SURFACE CHANNEL;

ALUMINUM; ELECTRON MOBILITY; GALLIUM; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTING INDIUM;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 77957564613     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2010.5551942     Document Type: Conference Paper

References (7)

1. Y. Sun et al, IEDM, 367, (2008).
2. M. Passlack et al, IEDM, 621, (2007).
3. H. Zhao et al, Appl. Phys. Lett. 94, 193502 (2009).
4. Y. Xuan et al, Electron. Dev. Lett., 29, 294, (2008).
5. N. Goel et al, IEDM, 363, (2008).
6. D. Kim et al, IEDM, 719, (2008).
7. M.Radosavljevic et al, IEDM, 319 (2009).