Fluorinated HfO2 gate dielectrics engineering for CMOS by pre-and post-CF4 plasma passivation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Wu, Woei Cherng ^a,b,c   Lai, Chao Sung ^a   Lee, Shih Ching ^b   Ming Wen, Ma ^c   Chao, Tien Sheng ^b   Wang, Jer Chyi ^b   Hsu, Chih Wei ^a   Chou, Pai Chi ^a   Chen, Jian Hao ^b   Kao, Kuo Hsing ^b   Lo, Wen Cheng ^a   Lu, Tsung Yi ^b   Tay, Li Lin ^d   Rowell, Nelson ^d  

^a CHANG GUNG UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^d NATIONAL RESEARCH COUNCIL CANADA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS DEVICES; FLUORINATED HFO; HIGH ELECTRIC FIELDS; MOS FETS; PHYSICAL MODELS; PLASMA PASSIVATIONS; TRAPPING LEVELS;

ELECTRIC FIELDS; ELECTRON DEVICES; FLUORINE; GATE DIELECTRICS; GATES (TRANSISTOR); HOLE MOBILITY; PASSIVATION;

HAFNIUM COMPOUNDS;

EID: 64549144140     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796706     Document Type: Conference Paper

References (7)

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2. th Control and Its Impact on Reliability for Poly-Si Gate pFET," in IEDM Tech. Dig., pp. 17.1.1-17.1.4. 2005.
3. 2) Reliability by Incorporation of Fluorine," in IEDM Tech. Dig., pp. 17.2.1-17.2.4. 2005.
4. Y. Yasuda, et al., "Effect of Fluorine Incorporation on 1/f Noise of HfSiON FETs for Future Mixed-Signal CMOS," in IEDM Tech. Dig., pp. 10.5.1-10.5.4. 2006.
5. 2/IL/Si Structure with Silicon Surface Fluorine Implantation (SSFI)," IEEE Trans. Electron Devices, vol. 55, pp. 1639-1646, 2008.
6. 4 Plasma Treatment," Appl. Phys. Lett., vol. 89, pp. 072904-072906, 2006.
7. 2 Gate Dielectrics with TaN Metal Gate," Appl. Phys. Lett. vol. 86, pp. 22905-22907, 2005.