Transistor-level synthesis of pipeline analog-to-digital converters using a design-space reduction algorithm

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 12, 2011, Pages 2816-2828

  Ruiz Amaya, Jesús ^a   Delgado Restituto, Manuel ^a   Rodríguez Vázquez, Ángel ^a  

^a UNIVERSITY OF SEVILLE   (Spain)

Author keywords

Design methodology; pipeline data converters

Indexed keywords

ENERGY EFFICIENCY; ENERGY UTILIZATION; PIPELINES; SPECIFICATIONS;

COMPUTATIONAL COSTS; DESIGN METHODOLOGY; EFFECTIVE RESOLUTIONS; OPTIMIZATION ROUTINE; PIPELINE ANALOG-TO-DIGITAL CONVERTERS; PIPELINE ARCHITECTURE; PIPELINE DATA CONVERTERS; SYNTHESIS PROCEDURE;

ANALOG TO DIGITAL CONVERSION;

EID: 82555165065     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2011.2157746     Document Type: Article

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