A 15-bit linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 2, 2008, Pages 342-350

  Shu, Yun Shiang ^a,b   Song, Bang Sup ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Background calibration; Capacitor mismatch and gain calibration; Digital calibration; Pipelined analog to digital converter; Signal dependent dithering

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITORS; MULTIPLYING CIRCUITS; SIGNAL TO NOISE RATIO;

BACKGROUND CALIBRATION; CAPACITOR MISMATCH; GAIN CALIBRATION; OPAMP GAIN ERRORS;

ELECTRIC SIGNAL SYSTEMS;

EID: 38849172488     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.914260     Document Type: Article

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