A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1047-1056

  Van De Vel, Hans ^a   Buter, Berry A J ^a   Van Der Ploeg, Hendrik ^b   Vertregt, Maarten ^a   Geelen, Govert J G M ^a   Paulus, Edward J F ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b Catena Radio Design   (Netherlands)

Author keywords

ADC; Analog to digital conversion; Calibration; Charge reset; CMOS analog integrated circuits; Low power; Low voltage; Pipeline; range scaling

Indexed keywords

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; CALIBRATION; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; MULTICARRIER MODULATION; PIPELINES; TIME VARYING SYSTEMS;

ADC; CHARGE RESET; CMOS ANALOG INTEGRATED CIRCUITS; LOW POWER; LOW VOLTAGE; RANGE SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 63449097619     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014702     Document Type: Conference Paper

References (17)

1. K. C. Zangi and R. D. Koilpillai, "Software radio issues in cellular base stations," IEEE J. Select. Areas Commun., vol. 17, pp. 561-573, Apr. 1999.
2. W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, "A 3-V 340-m.W 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931-1936, Dec. 2001.
3. B.-G. Lee, B.-M. Min, G. Manganaro, and J. W. Valvano, "A 14b 100 MS/s pipelined ADC with a merged active S/H and first MDAC," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 248-249.
4. S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter," IEEE J. Solid-State Circuits, vol. SC-22, no. 12, pp. 954-961, Dec. 1987.
5. H. Van de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen, and E. Paulus, "A 1.2 V 250mW 14b 100 MS/s digitally calibrated pipeline ADC in 90 nm CMOS," in VLSI Circuits Symp. Dig., Jun. 2008, pp. 74-75.
6. A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, "Analog circuits in ultra-deep-submicron CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 132-143, Jan. 2005.
7. A. M. Abo and P. R. Gray, "A 1.5-V, 10-b, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
8. B. Murmann, "Digitally assisted analog circuits," IEEE Micro, vol. 26, pp. 38-47, Mar. 2006.
9. B.-S. Song, S.-H. Lee, and M. F. Tompsett, "A 10-b 15-MHz CMOS recycling two-step A/D converter," IEEE J. Solid-State Circuits, vol. 25, no. 12, pp. 1328-1338, Dec. 1990.
10. 2 90-nm CMOS pipeline ADC for flat panel display applications," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2688-2695, Dec. 2007.
11. K. Bult, "Analog design in deep sub-micron CMOS," in Proc. ESSCIRC, Sep. 2000, pp. 126-132.
12. S. Limotyrakis, S. D. Kulchycki, D. K. Su, and B. A. Wooley, "A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1057-1067, May 2005.
13. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
14. 2 with mixed-signal chopping and calibration," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1859-1867, Dec. 2001.
15. H. van der Ploeg and B. Nauta, Calibration Techniques in Nyquist A/D Converters. New York: Springer, 2006.
16. G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor, and R. Verluden, "A 90 nm CMOS 1.2 V 10b power and speed programmable pipelined ADC with 0.5 pJ/conversion-step," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 214-215.
17. 2 10b 30 MS/s pipelined ADC without a front-end S/H in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 456-457.