A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 883-890

  Iizuka, Kunihiko ^a,b   Matsui, Hirofumi ^b   Ueda, Masaya ^b   Daito, Mutsuo ^b  

^a IEEE   (Japan)

^b SHARP CORPORATION   (Japan)

Author keywords

Adaptive system; Analog to digital (A D) converters; Analog to digital conversion (ADC); Calibration; CMOS analog integrated circuits; CMOS integrated circuits; Optimization; Pipeline processing

Indexed keywords

ADAPTIVE SYSTEM; ANALOG-TO-DIGITAL (A/D) CONVERTERS; CMOS ANALOG INTEGRATED CIRCUITS; PIPELINE PROCESSING;

ADAPTIVE SYSTEMS; AMPLIFIERS (ELECTRONIC); CALIBRATION; CMOS INTEGRATED CIRCUITS; OPTIMIZATION; VOLTAGE CONTROL;

ANALOG TO DIGITAL CONVERSION;

EID: 33645669128     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870788     Document Type: Conference Paper

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