A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 4, 2006, Pages 795-801

  Kim, Hwi Cheol ^a   Jeong, Deog Kyoon ^a   Kim, Wonchan ^a  

^a School of Electrical Engineering Seoul National University   (South Korea)

Author keywords

Analog to digital conversion; High speed; Low power; Partially switched opamp; Pipelined analog to digital converter; Power reduction; Switched opamp

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; ELECTRIC DISTORTION; ELECTRIC POWER SYSTEMS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; SWITCHING;

PARTIALLY SWITCHED OPAMP; PIPELINED ANALOG-TO-DIGITAL CONVERTER; POWER REDUCTION;

ANALOG TO DIGITAL CONVERSION;

EID: 33645816346     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.862070     Document Type: Article

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