A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 730-738

  Wu, Patrick Y ^b   Cheung, Vincent Sin Luen ^c   Luong, Howard C ^a,b  

^a IEEE

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^c Pericom Technology Incorporated   (Hong Kong)

Author keywords

ADC; Double sampling; High speed; Low voltage; Pipelined; Switched capacitor; Switched opamp

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CAPACITORS; ELECTRIC POTENTIAL;

DUAL-INPUT-DUAL-OUTPUT SWITCHABLE OPAMP; LOW VOLTAGE; SWITCHED CAPACITORS; SWITCHED-OPAMP (SO) TECHNIQUE;

CMOS INTEGRATED CIRCUITS;

EID: 33947653265     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.891666     Document Type: Article

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