-
1
-
-
28144436584
-
A 25 Gb/s PAM4 transmitter in 90 nm CMOS SOI
-
Feb.
-
C. Menolfi, T. Toifl, R. Reutemann, M. Ruegg, P. Buchmann, M. Kossel, T. Morf, and M. Schmatz, "A 25 Gb/s PAM4 transmitter in 90 nm CMOS SOI," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 72-73.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 72-73
-
-
Menolfi, C.1
Toifl, T.2
Reutemann, R.3
Ruegg, M.4
Buchmann, P.5
Kossel, M.6
Morf, T.7
Schmatz, M.8
-
2
-
-
0037344322
-
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25 μm CMOS
-
Mar.
-
J. T. Stonick, G.-Y. Wei, J. L. Sonntag, and D. K. Weinlader, "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25 μm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 436-443, Mar. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.3
, pp. 436-443
-
-
Stonick, J.T.1
Wei, G.-Y.2
Sonntag, J.L.3
Weinlader, D.K.4
-
3
-
-
9144245616
-
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell
-
Dec.
-
J. L. Zerbe, C. W. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim W. F. Stonecypher, A. Ho, T. P. Thrush, R. T. Kollipara, M. A. Horowitz, and K. S. Donnelly, "Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130, Dec. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.12
, pp. 2121-2130
-
-
Zerbe, J.L.1
Werner, C.W.2
Stojanovic, V.3
Chen, F.4
Wei, J.5
Tsang, G.6
Kim, D.7
Stonecypher, W.F.8
Ho, A.9
Thrush, T.P.10
Kollipara, R.T.11
Horowitz, M.A.12
Donnelly, K.S.13
-
4
-
-
0035505542
-
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS
-
Nov.
-
C. -K. K. Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick, "A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1684-1692, Nov. 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.11
, pp. 1684-1692
-
-
Yang, C.K.K.1
Stojanovic, V.2
Modjtahedi, S.3
Horowitz, M.A.4
Ellersick, W.F.5
-
5
-
-
0036113497
-
A 6 b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination
-
Feb.
-
P. Scholten and M. Vertregt, "A 6 b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination," in IEEE ISSCC Dig, Tech. Papers, vol. 1, Feb. 2002, pp. 168-457.
-
(2002)
IEEE ISSCC Dig, Tech. Papers
, vol.1
, pp. 168-457
-
-
Scholten, P.1
Vertregt, M.2
-
6
-
-
13444283710
-
A 1-GHz signal bandwidth 6-bit CMOS with power efficient averaging
-
Feb.
-
X. Jiang and M. F. Chang, "A 1-GHz signal bandwidth 6-bit CMOS with power efficient averaging," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 532-535, Feb. 2005.
-
(2005)
IEEE J. Solid-state Circuits
, vol.40
, Issue.2
, pp. 532-535
-
-
Jiang, X.1
Chang, M.F.2
-
7
-
-
0035058178
-
A6b 1.1 Gsample/s CMOS A/D converter
-
Feb.
-
G. Geelen, "A6b 1.1 Gsample/s CMOS A/D converter," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 128-129.
-
(2001)
IEEE ISSCC Dig. Tech. Papers
, pp. 128-129
-
-
Geelen, G.1
-
8
-
-
0037630792
-
A 20 GS/s 8 b ADC with a 1 MB memory in 0.18-μm CMOS
-
Feb.
-
K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montij, "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18-μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 318-496.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 318-496
-
-
Poulton, K.1
Neff, R.2
Setterberg, B.3
Wuppermann, B.4
Kopley, T.5
Jewett, R.6
Pernillo, J.7
Tan, C.8
Montij, A.9
-
9
-
-
2442637540
-
A 1.8 v 1.6 GS/S 8b self-calibrating folding ADC with 7.26 ENOB at nyquist frequency
-
Feb.
-
R.Taft, C. Menkus, M. R. Tursi, O. Hidri, and V. Pons,"A 1.8 V 1.6 GS/S 8b self-calibrating folding ADC with 7.26 ENOB at nyquist frequency," in IEEE ISSCC Dig. Tech. Papers, vol. 1, Feb. 2004, pp. 252-526.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, vol.1
, pp. 252-526
-
-
Taft, R.1
Menkus, C.2
Tursi, M.R.3
Hidri, O.4
Pons, V.5
-
11
-
-
0026836960
-
A 10-b 20-Msample/s analog-to-digital converter
-
Mar.
-
S. H. Lewis, H. S. Fetterman, G. F. Gross, R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, Issue.3
, pp. 351-358
-
-
Lewis, S.H.1
Fetterman, H.S.2
Gross, G.F.3
Ramachandran, R.4
Viswanathan, T.R.5
-
13
-
-
0029269932
-
A 10 b, 20 Msamples/s, 35 mW pipeline A/D converter
-
Mar.
-
T. Cho and P. R. Gray, "A 10 b, 20 Msamples/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
-
(1995)
IEEE J. Solid-state Circuits
, vol.30
, Issue.3
, pp. 166-172
-
-
Cho, T.1
Gray, P.R.2
-
14
-
-
0242551728
-
Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL
-
Nov.
-
J. G. Maneatis, J. Kim, L. McClatchie, J. Maxey, and M. Shankaradas, "Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.11
, pp. 1795-1803
-
-
Maneatis, J.G.1
Kim, J.2
McClatchie, L.3
Maxey, J.4
Shankaradas, M.5
-
15
-
-
0022769699
-
Reference refreshing cyclic analog-to-digital and digital-to-analog converters
-
Aug.
-
C.-C. Shih and P. R. Gray, "Reference refreshing cyclic analog-to-digital and digital-to-analog converters," IEEE J. Solid-State Circuits, vol. SC-21, no. 4, pp. 544-554, Aug. 1986.
-
(1986)
IEEE J. Solid-state Circuits
, vol.SC-21
, Issue.4
, pp. 544-554
-
-
Shih, C.-C.1
Gray, P.R.2
-
16
-
-
0035473398
-
An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration
-
Oct.
-
J. Ming and S. H. Lewis, "An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1489-1497, Oct. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.36
, Issue.10
, pp. 1489-1497
-
-
Ming, J.1
Lewis, S.H.2
-
17
-
-
2442692681
-
A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS
-
Feb.
-
D. Draxelmayr, "A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, vol. 1, Feb. 2004, pp. 264-527.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, vol.1
, pp. 264-527
-
-
Draxelmayr, D.1
-
18
-
-
4544256290
-
A 600 MS/s 5-bit pipelined analog-to-digital converter for serial-link applications
-
Jun.
-
A. Varzaghani and C. -K. K. Yang, "A 600 MS/s 5-bit pipelined analog-to-digital converter for serial-link applications," in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, Jun. 2004, pp. 276-279.
-
(2004)
IEEE Symp. VLSI Circuits, Dig. Tech. Papers
, pp. 276-279
-
-
Varzaghani, A.1
Yang, C.K.K.2
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