A 14-bit 20-MS/s pipelined ADC with digital distortion calibration

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2417-2423

  Daito, Mutsuo ^b   Matsui, Hirofumi ^b   Ueda, Masaya ^b   Iizuka, Kunihiko ^a,b  

^a IEEE   (Japan)

^b SHARP CORPORATION   (Japan)

Author keywords

Analog to digital converter (ADC); Calibration; CMOS analog integrated circuits; Distortion

Indexed keywords

CMOS ANALOG INTEGRATED CIRCUITS; DIGITAL DISTORTION CALIBRATION; DIGITAL GAIN CALIBRATION;

CALIBRATION; CMOS INTEGRATED CIRCUITS; GAIN CONTROL; HARMONIC ANALYSIS; SIGNAL DISTORTION;

ANALOG TO DIGITAL CONVERSION;

EID: 33750836390     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.882886     Document Type: Conference Paper

References (14)

1. H. Chen, B. Son, and K. Bacrania, "A 14-b 20 MSamples/s CMOS pipelined ADC," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 997-1001, Jun. 2001.
2. Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 2004.
3. A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, "A 15-b 1-MSample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, ser. 12, vol. 28, pp. 1207-1215, Dec. 1993.
4. S. Y. Chuang and T. L. Sculley, "A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 674-683, Jun. 2002.
5. J. Ming and S. H. Lewis, "An 8-bit 80-Msample/s pipelined analog-to-digtal converter with background calibration," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1489-1497, Dec. 2001.
6. E. Siragursa and I. Gallon, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, Dec. 2004.
7. B. Murman and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
8. C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12b 80 MS/s pipelined ADC with bootstrapped digital calibration," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 460-461.
9. K. Iizuka, H. Matsui, M. Ueda, and M. Daito, "A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/S," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 883-890, Apr. 2006.
10. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
11. W. Sansen, "Distortion in elementary transistor circuits," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 3, pp. 315-325, Mar. 1999.
12. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proc. IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996.
13. G. Nicollini, P. Confalonieri, and D. Senderowicz, "A fully differential sample-and-hold circuit for high-speed applications," IEEE J. Solid-State Circuits, vol. 24, no. 10, pp. 1461-1465, Oct. 1989.
14. A. M. Abo and P. R. Gray, "A 1.5 V, 10-bit, 14.3-MS/s CMOS pipelined analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.