Accurate settling-time modeling and design procedures for two-stage miller-compensated amplifiers for switched-capacitor circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 6, 2009, Pages 1077-1087

  Ruiz Amaya, Jesús ^a   Delgado Restituto, Manuel ^a   Rodríguez Vázquez, Ángel ^a  

^a UNIVERSITY OF SEVILLE   (Spain)

Author keywords

Analog circuit design; Data converters; Design methodology; Operational amplifiers; Switched capacitor (SC) circuits

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; OPERATIONAL AMPLIFIERS; SPECIFICATIONS; TIMING CIRCUITS;

ANALOG CIRCUIT DESIGN; BEHAVIORAL APPROACHES; BEHAVIORAL DESCRIPTIONS; DATA CONVERTER; DESIGN METHODOLOGY; ELECTRICAL SIMULATION; SWITCHED CAPACITOR CIRCUITS; SYSTEM-LEVEL SPECIFICATIONS;

STRUCTURAL DESIGN;

EID: 67650469694     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2008509     Document Type: Article

References (23)

1. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
2. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed. New York: Oxford Univ. Press, 2002.
3. A. Rodríguez-Vázquez, F. Medeiro, and E. Janssens, Eds., CMOS Telecom Data Converters. Dordrecht, The Netherlands: Kluwer Academic, 2003.
4. F. Maloberti, Data Converters. Dordrecht, The Netherlands: Springer, 2007.
5. P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Integrated Circuits, 4th ed. New York: Wiley, 2001.
6. F. Medeiro, B. Pérez-Verdú, A. Rodríguez-Vázquez, and J. L. Huertas, "A vertically integrated tool for automated design of SD modulators," IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 762-772, Jul. 1995.
7. R. A. Rutenbar, G. G. E. Gielen, and J. Roychowdhury, "Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs," Proc. IEEE, vol. 95, no. 3, pp. 640-669, Mar. 2007.
8. W. Kruiskamp and D. Leenaerts, "DARWIN: CMOS Opamp synthesis by means of a genetic algorithm," in Proc. 32nd ACM/IEEE Design Automation Conf, Jun. 1995, pp. 433-439.
9. M. M. Hershenson and S. Boyd, "GPCAD: A tool for CMOS Op-Amp synthesis," in Proc. 35th IEEE/ACM Int. Conf. CAD, Nov. 1998, pp. 296-303.
10. H. Koh, C. H. Sequin, and P. R. Gray, "OPASYN: A compiler for CMOS operational amplifiers," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 2, pp. 113-125, Feb. 1990.
11. J. Yuan, N. Farhat, and J. Van der Spiegel, "GBOPCAD: A synthesis tool for high-performance gain-boosted Opamp design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 1535-1544, Aug. 2005.
12. P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, F. Cusinato, and A. Baschirotto, "Behavioral modeling of switched-capacitor sigma-delta modulators," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 3, pp. 352-364, Mar. 2003.
13. H. Aminzadeh, M. Danaie, and R. Lotfi, "Design of two-stage Miller-compensated amplifiers based on an optimized settling model," in Proc. Int. Conf. VLSI Design, Jan. 2007, pp. 171-176.
14. C. T. Chuang, "Analysis of the settling behavior of an operational amplifier," IEEE J. Solid-State Circuits, vol. SC-17, no. 1, pp. 74-80, Feb. 1982.
15. H. C. Yang and D. J. Allstot, "Considerations for fast settling operational amplifiers," IEEE Trans. Circuits Syst., vol. 37, no. 3, pp. 326-334, Mar. 1990.
16. C. Azzolini, P. Milanesi, and A. Boni, "Accurate transient response model for automatic synthesis of high-speed operational amplifiers," in Proc. IEEE Int. Symp.Circ. Sys, May 2006, pp. 5716-5719.
17. M. Yavari and O. Shoaei, "Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications," IEE Proc. Cir., Dev. Sys, vol. 151, pp. 573-578, Dec. 2004.
18. S. O. Cannizzaro, A. D. Grasso, R. Mita, G. Palumbo, and S. Pennisi, "Design procedures for three-stage CMOS OTAs with nested-Miller compensation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 933-940, May 2004.
19. B. Hernes and W. Sansen, "Distortion in single-, two- and three-stage amplifiers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 5, pp. 846-856, May 2005.
20. S. O. Cannizzaro, G. Palumbo, and S. Pennisi, "Distortion analysis of Miller-compensated three-stage amplifiers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 961-976, May 2006.
21. R. G. H. Eschauzier, L. P. T. Kerklaan, and J. H. Huijsing, "A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure," IEEE J. Solid-State Circuits, vol. 27, no. 6, pp. 1709-1717, Dec. 1992.
22. U. Chilakapari and T. S. Fiez, "Effect of switch resistance on the SC integrator settling time," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 810-816, Jun. 1999.
23. R. del Río, F. Medeiro, B. Pérez-Verdú, J. M. de la Rosa, and A. Rodríguez-Vázquez, CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom Error Analysis and Practical Design. Berlin, Germany: Springer, 2006.