A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS pipeline ADC for flat panel display applications

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 12, 2007, Pages 2688-2695

  Lee, Seung Chul ^a   Jeon, Young Deuk ^a   Kwon, Jong Kee ^a   Kim, Jongdae ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Amplifiers; Analog to digital converter (ADC); Buffer circuits; CMOS analog integrated circuits; Integrated circuit testing; Low drop out regulator; Low power; Low voltage; Noise measurement; Pipeline stage optimization; Power supply rejection ratio (PSRR); Sample and hold (S H) circuits; Switched capacitor circuits

Indexed keywords

AMPLIFIERS; ANALOG TO DIGITAL CONVERTERS; CMOS ANALOG INTEGRATED CIRCUITS; LOW DROPOUT REGULATOR; LOW POWER; LOW VOLTAGES; NOISE MEASUREMENTS; POWER SUPPLY REJECTION RATIO; SAMPLE-AND-HOLD CIRCUITS; SWITCHED CAPACITOR CIRCUITS;

ACOUSTIC NOISE MEASUREMENT; ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; BUFFER AMPLIFIERS; BUFFER CIRCUITS; CAPACITORS; DIGITAL INTEGRATED CIRCUITS; DROPS; FLAT PANEL DISPLAYS; FREQUENCY CONVERTERS; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; OPTIMIZATION; PIPELINES; TRANSCONDUCTANCE;

CMOS INTEGRATED CIRCUITS;

EID: 57849140436     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.908760     Document Type: Conference Paper

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