Optimization of the nonoverlap length in decanano MOS devices with 2-D QM simulations

IEEE Transactions on Electron Devices

Volumn 51, Issue 11, 2004, Pages 1849-1855

  Gusmeroli, Ricardo ^a   Spinelli, Alessandro S ^b   Pirovano, Agostino ^c   Lacaita, Andrea L ^a   Boeuf F ^d   Skotnicki, Thomas ^d  

^a IFN CNR   (Italy)

^b UNIVERSITY OF INSUBRIA   (Italy)

^c STMICROELECTRONICS   (Italy)

^d STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; MOSFET DEVICES; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SENSITIVITY ANALYSIS; TWO DIMENSIONAL;

DECANANO MOS DEVICES; QUANTIZATION; QUANTUM MECHANICAL SIMULATION; SOURCE DRAIN (SD) OVERLAP;

MOS DEVICES;

EID: 8144230593     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.837124     Document Type: Article

References (30)

1. "Session 3," IEDM Tech. Dig., pp. 57-80, 2002.
2. International Technology Roadmap for Semiconductors, 2003.
3. B. Yu et al., "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
4. F.-L. Yang et al., "25 nm CMOS omega FET," in IEDM Tech. Dig., 2002, pp. 255-258.
5. S. Harrison et al., "Highly performant double gate MOSFET realized with SON process," in IEDM Tech. Dig., 2003, pp. 449-452.
6. F. Bœuf et al., "16-nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimization," in IEDM Tech. Dig., 2001, pp. 637-640.
7. A. Hokazono et al., "14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide," in IEDM Tech. Dig., 2002, pp. 639-642.
8. K. Goto et al., "High performance 25-nm gate CMOSFETs for 65-nm node high speed MPUs," in IEDM Tech. Dig., 2003, pp. 623-626.
9. S. Datta, "Nanoscale device modeling: The Greens function method," Superlatt. Microstruct., vol. 28, pp. 253-278, 2000.
10. Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, and J. Fossum, "The ballistic nanotransistor: A simulation study," in IEDM Tech. Dig., 2000, pp. 715-718.
11. Z. Ren, R. Venugopal, S. Datta, and M. Lundstrom, "Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Greens function formalism," in IEDM Tech. Dig., 2001, pp. 107-110.
12. J. Wang and M. Lundstrom, "Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?," in IEDM Tech. Dig., 2002, pp. 707-710.
13. A. Svizhenko, M. P. Anantram, T. R. Govindam, B. Biegel, and R. Venugopal, "Two-dimensional quantum-mechanical modeling of nanotransistors," J. Appl. Phys., vol. 91, pp. 2343-2354,2002.
14. G. Fiori and G. Iannaccone, "Modeling of ballistic nanoscale metal-oxide-semiconductor field effect transistors," Appl. Phys. Lett., vol. 81, pp. 3672-3674, 2002.
15. A. Wettstein, A. Schenk, and W. Fichtner, "Quantum device simulation with the density-gradient model on unstructured grids," IEEE Trans. Electron Devices, vol. 48, pp. 279-284, Feb. 2001.
16. A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, " Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm-MOSFETs due to quantum effects: A 3-D density-gradient simulation study," IEEE Trans. Electron Devices, vol. 48, pp. 722-729, Apr. 2001.
17. D. Connelly, Z. Yu, and D. Yergeau, "Macroscopic simulation of quantum mechanical effects in 2-D MOS devices via the density gradient method," IEEE Trans. Electron Devices, vol. 49, pp. 619-626, Apr. 2002.
18. A. Abramo, A. Cardin, L. Selmi, and E. Sangiorgi, "Two-dimensional quantum mechanical simulation of charge distribution in silicon MOSFETs," IEEE Trans. Electron Devices, vol. 47, pp. 1858-1863, Oct. 2000.
19. A. Pirovano, A. L. Lacaita, and A. Spinelli, "Two dimensional quantum effects in nanoscale MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 25-31, Jan. 2002.
20. S. Thompson et al., "Source/drain extension scaling for 0.1 μm and below channel length MOSFETS," in Symp. VLSI Tech. Dig., 1998, pp. 132-133.
21. T. Ghani et al., "Scaling challenges and device design requirements for high-performance sub-50 nm gate length planar CMOS transistors," in Symp. VLSI Tech. Dig., 2000, pp. 174-175.
22. T. Ghani et al., "Asymmetric source/drain extension transistor structure for high-performance sub-50 nm gate length CMOS devices," in Symp. VLSI Tech. Dig., 2001, pp. 17-18.
23. H. Lee, J. Lee, and H. Shin, "DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure," IEEE Trans. Nanotech., vol. 1, pp. 219-225, Dec. 2002.
24. H. Beneking and H. Kasugai, "Gigahertz p-channel enhancement silicon MOSFET with nonoverlapping gate," IEEE J. Solid-State Circuits, vol. 5, pp. 328-330, Dec. 1970.
25. J. G. Fossum, M. M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, "Physical insight on design and modeling of nanoscale FinFETs," in IEDM Tech. Dig., 2003, pp. 679-682.
26. A. Svizhenko and M. P. Anantram, "Role of scattering in nanotransistors," IEEE Trans. Electron Devices, vol. 50, pp. 1459-1466, June 2003.
27. M. V. Fischetti, S. E. Laux, and A. Kumar, "Simulation of quantum electronic transport in small devices: A master equation approach," in IEDM Tech. Dig., 2003, pp. 467-470.
28. S. Villa, A. L. Lacaita, L. M. Perron, and R. Bez, "A physically-based model of the effective mobility in heavily doped n-MOSFETs," IEEE Trans. Electron Devices, vol. 45, pp. 110-115, Jan. 1998.
29. A. S. Spinelli, A. Benvenuti, S. Villa, and A. L. Lacaita, "MOSFET simulation with quantum effects and nonlocal mobility model," IEEE Electron Dev. Lett., vol. 20, pp. 298-300, June 1999.
30. R. Gusmeroli, A. S. Spinelli, A. Pirovano, A. L. Lacaita, F. Bœuf, and T. Skotnicki, "2-D QM simulation and optimization of decanano nonoverlapped MOS devices," in IEDM Tech. Dig., 2003, pp. 225-228.